Attachment #49551 for bug #30144

View Details Raw Unified Return to Bug 30144

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2010-02-25  Chao-ying Fu  <fu@mips.com>

        Reviewed by NOBODY (OOPS!).

        MIPS JIT Supports
        https://bugs.webkit.org/show_bug.cgi?id=30144

	The following changes are for MIPS JIT.

        * assembler/AbstractMacroAssembler.h:
        (JSC::AbstractMacroAssembler::Imm32::Imm32):
        * assembler/MIPSAssembler.h: Added.
        (JSC::MIPSRegisters::):
        (JSC::MIPSAssembler::MIPSAssembler):
        (JSC::MIPSAssembler::):
        (JSC::MIPSAssembler::JmpSrc::JmpSrc):
        (JSC::MIPSAssembler::JmpDst::JmpDst):
        (JSC::MIPSAssembler::JmpDst::isUsed):
        (JSC::MIPSAssembler::JmpDst::used):
        (JSC::MIPSAssembler::emitInst):
        (JSC::MIPSAssembler::nop):
        (JSC::MIPSAssembler::loadDelayNop):
        (JSC::MIPSAssembler::copDelayNop):
        (JSC::MIPSAssembler::move):
        (JSC::MIPSAssembler::li):
        (JSC::MIPSAssembler::lui):
        (JSC::MIPSAssembler::addiu):
        (JSC::MIPSAssembler::addu):
        (JSC::MIPSAssembler::subu):
        (JSC::MIPSAssembler::mult):
        (JSC::MIPSAssembler::mfhi):
        (JSC::MIPSAssembler::mflo):
        (JSC::MIPSAssembler::mul):
        (JSC::MIPSAssembler::andInsn):
        (JSC::MIPSAssembler::andi):
        (JSC::MIPSAssembler::nor):
        (JSC::MIPSAssembler::orInsn):
        (JSC::MIPSAssembler::ori):
        (JSC::MIPSAssembler::xorInsn):
        (JSC::MIPSAssembler::xori):
        (JSC::MIPSAssembler::slt):
        (JSC::MIPSAssembler::sltu):
        (JSC::MIPSAssembler::sltiu):
        (JSC::MIPSAssembler::sll):
        (JSC::MIPSAssembler::sllv):
        (JSC::MIPSAssembler::sra):
        (JSC::MIPSAssembler::srav):
        (JSC::MIPSAssembler::lw):
        (JSC::MIPSAssembler::lwl):
        (JSC::MIPSAssembler::lwr):
        (JSC::MIPSAssembler::lhu):
        (JSC::MIPSAssembler::sw):
        (JSC::MIPSAssembler::jr):
        (JSC::MIPSAssembler::jalr):
        (JSC::MIPSAssembler::jal):
        (JSC::MIPSAssembler::bkpt):
        (JSC::MIPSAssembler::bgez):
        (JSC::MIPSAssembler::bltz):
        (JSC::MIPSAssembler::beq):
        (JSC::MIPSAssembler::bne):
        (JSC::MIPSAssembler::bc1t):
        (JSC::MIPSAssembler::bc1f):
        (JSC::MIPSAssembler::newJmpSrc):
        (JSC::MIPSAssembler::appendJump):
        (JSC::MIPSAssembler::addd):
        (JSC::MIPSAssembler::subd):
        (JSC::MIPSAssembler::muld):
        (JSC::MIPSAssembler::lwc1):
        (JSC::MIPSAssembler::ldc1):
        (JSC::MIPSAssembler::swc1):
        (JSC::MIPSAssembler::sdc1):
        (JSC::MIPSAssembler::mtc1):
        (JSC::MIPSAssembler::mfc1):
        (JSC::MIPSAssembler::truncwd):
        (JSC::MIPSAssembler::cvtdw):
        (JSC::MIPSAssembler::ceqd):
        (JSC::MIPSAssembler::cngtd):
        (JSC::MIPSAssembler::cnged):
        (JSC::MIPSAssembler::cltd):
        (JSC::MIPSAssembler::cled):
        (JSC::MIPSAssembler::cueqd):
        (JSC::MIPSAssembler::coled):
        (JSC::MIPSAssembler::coltd):
        (JSC::MIPSAssembler::culed):
        (JSC::MIPSAssembler::cultd):
        (JSC::MIPSAssembler::label):
        (JSC::MIPSAssembler::align):
        (JSC::MIPSAssembler::getRelocatedAddress):
        (JSC::MIPSAssembler::getDifferenceBetweenLabels):
        (JSC::MIPSAssembler::size):
        (JSC::MIPSAssembler::executableCopy):
        (JSC::MIPSAssembler::getCallReturnOffset):
        (JSC::MIPSAssembler::linkJump):
        (JSC::MIPSAssembler::linkCall):
        (JSC::MIPSAssembler::linkPointer):
        (JSC::MIPSAssembler::relinkJump):
        (JSC::MIPSAssembler::relinkCall):
        (JSC::MIPSAssembler::repatchInt32):
        (JSC::MIPSAssembler::repatchPointer):
        (JSC::MIPSAssembler::repatchLoadPtrToLEA):
        (JSC::MIPSAssembler::relocateJumps):
        (JSC::MIPSAssembler::linkWithOffset):
        (JSC::MIPSAssembler::linkCallInternal):
        * assembler/MacroAssembler.h:
        * assembler/MacroAssemblerMIPS.h: Added.
        (JSC::MacroAssemblerMIPS::MacroAssemblerMIPS):
        (JSC::MacroAssemblerMIPS::):
        (JSC::MacroAssemblerMIPS::add32):
        (JSC::MacroAssemblerMIPS::and32):
        (JSC::MacroAssemblerMIPS::lshift32):
        (JSC::MacroAssemblerMIPS::mul32):
        (JSC::MacroAssemblerMIPS::not32):
        (JSC::MacroAssemblerMIPS::or32):
        (JSC::MacroAssemblerMIPS::rshift32):
        (JSC::MacroAssemblerMIPS::sub32):
        (JSC::MacroAssemblerMIPS::xor32):
        (JSC::MacroAssemblerMIPS::load32):
        (JSC::MacroAssemblerMIPS::load32WithUnalignedHalfWords):
        (JSC::MacroAssemblerMIPS::load32WithAddressOffsetPatch):
        (JSC::MacroAssemblerMIPS::loadPtrWithPatchToLEA):
        (JSC::MacroAssemblerMIPS::loadPtrWithAddressOffsetPatch):
        (JSC::MacroAssemblerMIPS::load16):
        (JSC::MacroAssemblerMIPS::store32WithAddressOffsetPatch):
        (JSC::MacroAssemblerMIPS::store32):
        (JSC::MacroAssemblerMIPS::supportsFloatingPoint):
        (JSC::MacroAssemblerMIPS::supportsFloatingPointTruncate):
        (JSC::MacroAssemblerMIPS::pop):
        (JSC::MacroAssemblerMIPS::push):
        (JSC::MacroAssemblerMIPS::move):
        (JSC::MacroAssemblerMIPS::swap):
        (JSC::MacroAssemblerMIPS::signExtend32ToPtr):
        (JSC::MacroAssemblerMIPS::zeroExtend32ToPtr):
        (JSC::MacroAssemblerMIPS::branch32):
        (JSC::MacroAssemblerMIPS::branch32WithUnalignedHalfWords):
        (JSC::MacroAssemblerMIPS::branch16):
        (JSC::MacroAssemblerMIPS::branchTest32):
        (JSC::MacroAssemblerMIPS::jump):
        (JSC::MacroAssemblerMIPS::branchAdd32):
        (JSC::MacroAssemblerMIPS::branchMul32):
        (JSC::MacroAssemblerMIPS::branchSub32):
        (JSC::MacroAssemblerMIPS::breakpoint):
        (JSC::MacroAssemblerMIPS::nearCall):
        (JSC::MacroAssemblerMIPS::call):
        (JSC::MacroAssemblerMIPS::ret):
        (JSC::MacroAssemblerMIPS::set32):
        (JSC::MacroAssemblerMIPS::setTest32):
        (JSC::MacroAssemblerMIPS::moveWithPatch):
        (JSC::MacroAssemblerMIPS::branchPtrWithPatch):
        (JSC::MacroAssemblerMIPS::storePtrWithPatch):
        (JSC::MacroAssemblerMIPS::tailRecursiveCall):
        (JSC::MacroAssemblerMIPS::makeTailRecursiveCall):
        (JSC::MacroAssemblerMIPS::loadDouble):
        (JSC::MacroAssemblerMIPS::storeDouble):
        (JSC::MacroAssemblerMIPS::addDouble):
        (JSC::MacroAssemblerMIPS::subDouble):
        (JSC::MacroAssemblerMIPS::mulDouble):
        (JSC::MacroAssemblerMIPS::convertInt32ToDouble):
        (JSC::MacroAssemblerMIPS::insertRelaxationWords):
        (JSC::MacroAssemblerMIPS::branchTrue):
        (JSC::MacroAssemblerMIPS::branchFalse):
        (JSC::MacroAssemblerMIPS::branchEqual):
        (JSC::MacroAssemblerMIPS::branchNotEqual):
        (JSC::MacroAssemblerMIPS::branchDouble):
        (JSC::MacroAssemblerMIPS::branchTruncateDoubleToInt32):
        (JSC::MacroAssemblerMIPS::linkCall):
        (JSC::MacroAssemblerMIPS::repatchCall):
        * jit/ExecutableAllocator.h:
        (JSC::ExecutableAllocator::cacheFlush):
        * jit/JIT.h:
        * jit/JITInlineMethods.h:
        (JSC::JIT::preserveReturnAddressAfterCall):
        (JSC::JIT::restoreReturnAddressBeforeReturn):
        * jit/JITOpcodes.cpp:
        * jit/JITStubs.cpp:
        (JSC::JITThunks::JITThunks):
        * jit/JITStubs.h:
        (JSC::JITStackFrame::returnAddressSlot):
        * wtf/Platform.h:
        * yarr/RegexJIT.cpp:
        (JSC::Yarr::RegexGenerator::generateEnter):
        (JSC::Yarr::RegexGenerator::generateReturn):

2010-02-25  Oliver Hunt  <oliver@apple.com>

        Reviewed by Geoff Garen.



    struct Imm32 {
        explicit Imm32(int32_t value)
            : m_value(value)
#if CPU(ARM) || CPU(MIPS)
            , m_isPointer(false)
#endif
        {

#if !CPU(X86_64)
        explicit Imm32(ImmPtr ptr)
            : m_value(ptr.asIntptr())
#if CPU(ARM) || CPU(MIPS)
            , m_isPointer(true)
#endif
        {

#endif

        int32_t m_value;
#if CPU(ARM) || CPU(MIPS)
        // We rely on being able to regenerate code to recover exception handling
        // information.  Since ARMv7 supports 16-bit immediates there is a danger
        // that if pointer values change the layout of the generated code will change.
        // To avoid this problem, always generate pointers (and thus Imm32s constructed
        // from ImmPtrs) with a code sequence that is able  to represent  any pointer
        // value - don't use a more compact form in these cases.
        // Same for MIPS.
        bool m_isPointer;
#endif
    };



/*
 * Copyright (C) 2009 Apple Inc. All rights reserved.
 * Copyright (C) 2009 University of Szeged
 * All rights reserved.
 * Copyright (C) 2009 MIPS Technologies, Inc. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY MIPS TECHNOLOGIES, INC. ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL MIPS TECHNOLOGIES, INC. OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef MIPSAssembler_h
#define MIPSAssembler_h

#include <wtf/Platform.h>
#include <wtf/SegmentedVector.h>

#if ENABLE(ASSEMBLER) && CPU(MIPS)

#include "AssemblerBuffer.h"
#include <wtf/Assertions.h>

namespace JSC {

typedef uint32_t MIPSWord;

namespace MIPSRegisters {
typedef enum {
    r0 = 0,
    r1,
    r2,
    r3,
    r4,
    r5,
    r6,
    r7,
    r8,
    r9,
    r10,
    r11,
    r12,
    r13,
    r14,
    r15,
    r16,
    r17,
    r18,
    r19,
    r20,
    r21,
    r22,
    r23,
    r24,
    r25,
    r26,
    r27,
    r28,
    r29,
    r30,
    r31,
    zero = r0,
    at = r1,
    v0 = r2,
    v1 = r3,
    a0 = r4,
    a1 = r5,
    a2 = r6,
    a3 = r7,
    t0 = r8,
    t1 = r9,
    t2 = r10,
    t3 = r11,
    t4 = r12,
    t5 = r13,
    t6 = r14,
    t7 = r15,
    s0 = r16,
    s1 = r17,
    s2 = r18,
    s3 = r19,
    s4 = r20,
    s5 = r21,
    s6 = r22,
    s7 = r23,
    t8 = r24,
    t9 = r25,
    k0 = r26,
    k1 = r27,
    gp = r28,
    sp = r29,
    fp = r30,
    ra = r31
} RegisterID;

typedef enum {
    f0,
    f1,
    f2,
    f3,
    f4,
    f5,
    f6,
    f7,
    f8,
    f9,
    f10,
    f11,
    f12,
    f13,
    f14,
    f15,
    f16,
    f17,
    f18,
    f19,
    f20,
    f21,
    f22,
    f23,
    f24,
    f25,
    f26,
    f27,
    f28,
    f29,
    f30,
    f31
} FPRegisterID;

} // namespace MIPSRegisters

class MIPSAssembler {
public:
    typedef MIPSRegisters::RegisterID RegisterID;
    typedef MIPSRegisters::FPRegisterID FPRegisterID;
    typedef SegmentedVector<int, 64> Jumps;

    MIPSAssembler()
    {
    }

    // MIPS instruction opcode field position
    enum {
        OP_SH_RD = 11,
        OP_SH_RT = 16,
        OP_SH_RS = 21,
        OP_SH_SHAMT = 6,
        OP_SH_CODE = 16,
        OP_SH_FD = 6,
        OP_SH_FS = 11,
        OP_SH_FT = 16
    };

    class JmpSrc {
        friend class MIPSAssembler;
    public:
        JmpSrc()
            : m_offset(-1)
        {
        }

    private:
        JmpSrc(int offset)
            : m_offset(offset)
        {
        }

        int m_offset;
    };

    class JmpDst {
        friend class MIPSAssembler;
    public:
        JmpDst()
            : m_offset(-1)
            , m_used(false)
        {
        }

        bool isUsed() const { return m_used; }
        void used() { m_used = true; }
    private:
        JmpDst(int offset)
            : m_offset(offset)
            , m_used(false)
        {
            ASSERT(m_offset == offset);
        }

        int m_offset : 31;
        int m_used : 1;
    };

    void emitInst(MIPSWord op)
    {
        void* oldBase = m_buffer.data();

        m_buffer.putInt(op);

        void* newBase = m_buffer.data();
        if (oldBase != newBase)
            relocateJumps(oldBase, newBase);
    }

    void nop()
    {
        emitInst(0x00000000);
    }

    /* Need to insert one load data delay nop for mips1.  */
    void loadDelayNop()
    {
#if WTF_MIPS_ISA(1)
        nop();
#endif
    }

    /* Need to insert one coprocessor access delay nop for mips1.  */
    void copDelayNop()
    {
#if WTF_MIPS_ISA(1)
        nop();
#endif
    }

    void move(RegisterID rd, RegisterID rs)
    {
        /* addu */
        emitInst(0x00000021 | (rd << OP_SH_RD) | (rs << OP_SH_RS));
    }

    /* Set an immediate value to a register.  This may generate 1 or 2
       instructions.  */
    void li(RegisterID dest, int imm)
    {
        if (imm >= -32768 && imm <= 32767)
            addiu(dest, MIPSRegisters::zero, imm);
        else if (imm >= 0 && imm < 65536)
            ori(dest, MIPSRegisters::zero, imm);
        else {
            lui(dest, imm >> 16);
            if (imm & 0xffff)
                ori(dest, dest, imm);
        }
    }

    void lui(RegisterID rt, int imm)
    {
        emitInst(0x3c000000 | (rt << OP_SH_RT) | (imm & 0xffff));
    }

    void addiu(RegisterID rt, RegisterID rs, int imm)
    {
        emitInst(0x24000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (imm & 0xffff));
    }

    void addu(RegisterID rd, RegisterID rs, RegisterID rt)
    {
        emitInst(0x00000021 | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
    }

    void subu(RegisterID rd, RegisterID rs, RegisterID rt)
    {
        emitInst(0x00000023 | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
    }

    void mult(RegisterID rs, RegisterID rt)
    {
        emitInst(0x00000018 | (rs << OP_SH_RS) | (rt << OP_SH_RT));
    }

    void mfhi(RegisterID rd)
    {
        emitInst(0x00000010 | (rd << OP_SH_RD));
    }

    void mflo(RegisterID rd)
    {
        emitInst(0x00000012 | (rd << OP_SH_RD));
    }

    void mul(RegisterID rd, RegisterID rs, RegisterID rt)
    {
#if WTF_MIPS_ISA_AT_LEAST(32) 
        emitInst(0x70000002 | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
#else
        mult(rs, rt);
        mflo(rd);
#endif
    }

    void andInsn(RegisterID rd, RegisterID rs, RegisterID rt)
    {
        emitInst(0x00000024 | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
    }

    void andi(RegisterID rt, RegisterID rs, int imm)
    {
        emitInst(0x30000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (imm & 0xffff));
    }

    void nor(RegisterID rd, RegisterID rs, RegisterID rt)
    {
        emitInst(0x00000027 | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
    }

    void orInsn(RegisterID rd, RegisterID rs, RegisterID rt)
    {
        emitInst(0x00000025 | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
    }

    void ori(RegisterID rt, RegisterID rs, int imm)
    {
        emitInst(0x34000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (imm & 0xffff));
    }

    void xorInsn(RegisterID rd, RegisterID rs, RegisterID rt)
    {
        emitInst(0x00000026 | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
    }

    void xori(RegisterID rt, RegisterID rs, int imm)
    {
        emitInst(0x38000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (imm & 0xffff));
    }

    void slt(RegisterID rd, RegisterID rs, RegisterID rt)
    {
        emitInst(0x0000002a | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
    }

    void sltu(RegisterID rd, RegisterID rs, RegisterID rt)
    {
        emitInst(0x0000002b | (rd << OP_SH_RD) | (rs << OP_SH_RS)
                 | (rt << OP_SH_RT));
    }

    void sltiu(RegisterID rt, RegisterID rs, int imm)
    {
        emitInst(0x2c000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (imm & 0xffff));
    }

    void sll(RegisterID rd, RegisterID rt, int shamt)
    {
        emitInst(0x00000000 | (rd << OP_SH_RD) | (rt << OP_SH_RT)
                 | ((shamt & 0x1f) << OP_SH_SHAMT));
    }

    void sllv(RegisterID rd, RegisterID rt, int rs)
    {
        emitInst(0x00000004 | (rd << OP_SH_RD) | (rt << OP_SH_RT)
                 | (rs << OP_SH_RS));
    }

    void sra(RegisterID rd, RegisterID rt, int shamt)
    {
        emitInst(0x00000003 | (rd << OP_SH_RD) | (rt << OP_SH_RT)
                 | ((shamt & 0x1f) << OP_SH_SHAMT));
    }

    void srav(RegisterID rd, RegisterID rt, RegisterID rs)
    {
        emitInst(0x00000007 | (rd << OP_SH_RD) | (rt << OP_SH_RT)
                 | (rs << OP_SH_RS));
    }

    void lw(RegisterID rt, RegisterID rs, int offset)
    {
        emitInst(0x8c000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
        loadDelayNop();
    }

    void lwl(RegisterID rt, RegisterID rs, int offset)
    {
        emitInst(0x88000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
        loadDelayNop();
    }

    void lwr(RegisterID rt, RegisterID rs, int offset)
    {
        emitInst(0x98000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
        loadDelayNop();
    }

    void lhu(RegisterID rt, RegisterID rs, int offset)
    {
        emitInst(0x94000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
        loadDelayNop();
    }

    void sw(RegisterID rt, RegisterID rs, int offset)
    {
        emitInst(0xac000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
    }

    void jr(RegisterID rs)
    {
        emitInst(0x00000008 | (rs << OP_SH_RS));
    }

    void jalr(RegisterID rs)
    {
        emitInst(0x0000f809 | (rs << OP_SH_RS));
    }

    void jal()
    {
        emitInst(0x0c000000);
    }

    void bkpt()
    {
        int value = 512; /* BRK_BUG */
        emitInst(0x0000000d | ((value & 0x3ff) << OP_SH_CODE));
    }

    void bgez(RegisterID rs, int imm)
    {
        emitInst(0x04010000 | (rs << OP_SH_RS) | (imm & 0xffff));
    }

    void bltz(RegisterID rs, int imm)
    {
        emitInst(0x04000000 | (rs << OP_SH_RS) | (imm & 0xffff));
    }

    void beq(RegisterID rs, RegisterID rt, int imm)
    {
        emitInst(0x10000000 | (rs << OP_SH_RS) | (rt << OP_SH_RT) | (imm & 0xffff));
    }

    void bne(RegisterID rs, RegisterID rt, int imm)
    {
        emitInst(0x14000000 | (rs << OP_SH_RS) | (rt << OP_SH_RT) | (imm & 0xffff));
    }

    void bc1t()
    {
        emitInst(0x45010000);
    }

    void bc1f()
    {
        emitInst(0x45000000);
    }

    JmpSrc newJmpSrc()
    {
        return JmpSrc(m_buffer.size());
    }

    void appendJump()
    {
        m_jumps.append(m_buffer.size());
    }

    void addd(FPRegisterID fd, FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200000 | (fd << OP_SH_FD) | (fs << OP_SH_FS)
                 | (ft << OP_SH_FT));
    }

    void subd(FPRegisterID fd, FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200001 | (fd << OP_SH_FD) | (fs << OP_SH_FS)
                 | (ft << OP_SH_FT));
    }

    void muld(FPRegisterID fd, FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200002 | (fd << OP_SH_FD) | (fs << OP_SH_FS)
                 | (ft << OP_SH_FT));
    }

    void lwc1(FPRegisterID ft, RegisterID rs, int offset)
    {
        emitInst(0xc4000000 | (ft << OP_SH_FT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
        copDelayNop();
    }

    void ldc1(FPRegisterID ft, RegisterID rs, int offset)
    {
        emitInst(0xd4000000 | (ft << OP_SH_FT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
    }

    void swc1(FPRegisterID ft, RegisterID rs, int offset)
    {
        emitInst(0xe4000000 | (ft << OP_SH_FT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
    }

    void sdc1(FPRegisterID ft, RegisterID rs, int offset)
    {
        emitInst(0xf4000000 | (ft << OP_SH_FT) | (rs << OP_SH_RS)
                 | (offset & 0xffff));
    }

    void mtc1(RegisterID rt, FPRegisterID fs)
    {
        emitInst(0x44800000 | (fs << OP_SH_FS) | (rt << OP_SH_RT));
        copDelayNop();
    }

    void mfc1(RegisterID rt, FPRegisterID fs)
    {
        emitInst(0x44000000 | (fs << OP_SH_FS) | (rt << OP_SH_RT));
        copDelayNop();
    }

    void truncwd(FPRegisterID fd, FPRegisterID fs)
    {
        emitInst(0x4620000d | (fd << OP_SH_FD) | (fs << OP_SH_FS));
    }

    void cvtdw(FPRegisterID fd, FPRegisterID fs)
    {
        emitInst(0x46800021 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
    }

    void ceqd(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200032 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void cngtd(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x4620003f | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void cnged(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x4620003d | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void cltd(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x4620003c | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void cled(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x4620003e | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void cueqd(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200033 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void coled(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200036 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void coltd(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200034 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void culed(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200037 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    void cultd(FPRegisterID fs, FPRegisterID ft)
    {
        emitInst(0x46200035 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
        copDelayNop();
    }

    // General helpers

    JmpDst label()
    {
        return JmpDst(m_buffer.size());
    }

    JmpDst align(int alignment)
    {
        while (!m_buffer.isAligned(alignment))
            bkpt();

        return label();
    }

    static void* getRelocatedAddress(void* code, JmpSrc jump)
    {
        ASSERT(jump.m_offset != -1);
        void* b = reinterpret_cast<void*>((reinterpret_cast<intptr_t>(code)) + jump.m_offset);
        return b;
    }

    static void* getRelocatedAddress(void* code, JmpDst label)
    {
        void* b = reinterpret_cast<void*>((reinterpret_cast<intptr_t>(code)) + label.m_offset);
        return b;
    }

    static int getDifferenceBetweenLabels(JmpDst from, JmpDst to)
    {
        return to.m_offset - from.m_offset;
    }

    static int getDifferenceBetweenLabels(JmpDst from, JmpSrc to)
    {
        return to.m_offset - from.m_offset;
    }

    static int getDifferenceBetweenLabels(JmpSrc from, JmpDst to)
    {
        return to.m_offset - from.m_offset;
    }

    // Assembler admin methods:

    size_t size() const
    {
        return m_buffer.size();
    }

    void* executableCopy(ExecutablePool* allocator)
    {
        void *result = m_buffer.executableCopy(allocator);
        if (!result)
            return 0;

        relocateJumps(m_buffer.data(), result);
        return result;
    }

    static unsigned getCallReturnOffset(JmpSrc call)
    {
        // The return address is after a call and a delay slot instruction
        return call.m_offset;
    }

    // Linking & patching:
    //
    // 'link' and 'patch' methods are for use on unprotected code - such as the code
    // within the AssemblerBuffer, and code being patched by the patch buffer.  Once
    // code has been finalized it is (platform support permitting) within a non-
    // writable region of memory; to modify the code in an execute-only execuable
    // pool the 'repatch' and 'relink' methods should be used.

    void linkJump(JmpSrc from, JmpDst to)
    {
        ASSERT(to.m_offset != -1);
        ASSERT(from.m_offset != -1);
        MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(m_buffer.data()) + from.m_offset);
        MIPSWord* toPos = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(m_buffer.data()) + to.m_offset);

        ASSERT(!(*(insn - 1)) && !(*(insn - 2)) && !(*(insn - 3)) && !(*(insn - 5)));
        insn = insn - 6;
        linkWithOffset(insn, toPos);
    }

    static void linkJump(void* code, JmpSrc from, void* to)
    {
        ASSERT(from.m_offset != -1);
        MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.m_offset);

        ASSERT(!(*(insn - 1)) && !(*(insn - 2)) && !(*(insn - 3)) && !(*(insn - 5)));
        insn = insn - 6;
        linkWithOffset(insn, to);
    }

    static void linkCall(void* code, JmpSrc from, void* to)
    {
        MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.m_offset);
        linkCallInternal(insn, to);
    }

    static void linkPointer(void* code, JmpDst from, void* to)
    {
        MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.m_offset);
        ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
        *insn = (*insn & 0xffff0000) | ((reinterpret_cast<intptr_t>(to) >> 16) & 0xffff);
        insn++;
        ASSERT((*insn & 0xfc000000) == 0x34000000); // ori
        *insn = (*insn & 0xffff0000) | (reinterpret_cast<intptr_t>(to) & 0xffff);
    }

    static void relinkJump(void* from, void* to)
    {
        MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);

        ASSERT(!(*(insn - 1)) && !(*(insn - 5)));
        insn = insn - 6;
        int flushSize = linkWithOffset(insn, to);

        ExecutableAllocator::cacheFlush(insn, flushSize);
    }

    static void relinkCall(void* from, void* to)
    {
        void* start;
        int size = linkCallInternal(from, to);
        if (size == sizeof(MIPSWord))
            start = reinterpret_cast<void*>(reinterpret_cast<intptr_t>(from) - 2 * sizeof(MIPSWord));
        else
            start = reinterpret_cast<void*>(reinterpret_cast<intptr_t>(from) - 4 * sizeof(MIPSWord));

        ExecutableAllocator::cacheFlush(start, size);
    }

    static void repatchInt32(void* from, int32_t to)
    {
        MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);
        ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
        *insn = (*insn & 0xffff0000) | ((to >> 16) & 0xffff);
        insn++;
        ASSERT((*insn & 0xfc000000) == 0x34000000); // ori
        *insn = (*insn & 0xffff0000) | (to & 0xffff);
        insn--;
        ExecutableAllocator::cacheFlush(insn, 2 * sizeof(MIPSWord));
    }

    static void repatchPointer(void* from, void* to)
    {
        repatchInt32(from, reinterpret_cast<int32_t>(to));
    }

    static void repatchLoadPtrToLEA(void* from)
    {
        MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);
        insn = insn + 3;
        ASSERT((*insn & 0xfc000000) == 0x8c000000); // lw
        /* lw -> addiu */
        *insn = 0x24000000 | (*insn & 0x03ffffff);

        ExecutableAllocator::cacheFlush(insn, sizeof(MIPSWord));
    }

private:

    /* Update each jump in the buffer of newBase.  */
    void relocateJumps(void* oldBase, void* newBase)
    {
        // Check each jump
        for (Jumps::Iterator iter = m_jumps.begin(); iter != m_jumps.end(); ++iter) {
            int pos = *iter;
            MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(newBase) + pos);
            insn = insn + 2;
            // Need to make sure we have 5 valid instructions after pos
            if ((unsigned int)pos >= m_buffer.size() - 5 * sizeof(MIPSWord))
                continue;

            if ((*insn & 0xfc000000) == 0x08000000) { // j
                int offset = *insn & 0x03ffffff;
                int oldInsnAddress = (int)insn - (int)newBase + (int)oldBase;
                int topFourBits = (oldInsnAddress + 4) >> 28;
                int oldTargetAddress = (topFourBits << 28) | (offset << 2);
                int newTargetAddress = oldTargetAddress - (int)oldBase + (int)newBase;
                int newInsnAddress = (int)insn;
                if (((newInsnAddress + 4) >> 28) == (newTargetAddress >> 28))
                    *insn = 0x08000000 | ((newTargetAddress >> 2) & 0x3ffffff);
                else {
                    /* lui */
                    *insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((newTargetAddress >> 16) & 0xffff);
                    /* ori */
                    *(insn + 1) = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (newTargetAddress & 0xffff);
                    /* jr */
                    *(insn + 2) = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS);
                }
            } else if ((*insn & 0xffe00000) == 0x3c000000) { // lui
                int high = (*insn & 0xffff) << 16;
                int low = *(insn + 1) & 0xffff;
                int oldTargetAddress = high | low;
                int newTargetAddress = oldTargetAddress - (int)oldBase + (int)newBase;
                /* lui */
                *insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((newTargetAddress >> 16) & 0xffff);
                /* ori */
                *(insn + 1) = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (newTargetAddress & 0xffff);
            }
        }
    }

    static int linkWithOffset(MIPSWord* insn, void* to)
    {
        ASSERT((*insn & 0xfc000000) == 0x10000000 // beq
               || (*insn & 0xfc000000) == 0x14000000 // bne
               || (*insn & 0xffff0000) == 0x45010000 // bc1t
               || (*insn & 0xffff0000) == 0x45000000); // bc1f
        intptr_t diff = (reinterpret_cast<intptr_t>(to)
                         - reinterpret_cast<intptr_t>(insn) - 4) >> 2;

        if (diff < -32768 || diff > 32767 || *(insn + 2) != 0x10000003) {
            /*
                Convert the sequence:
                  beq $2, $3, target
                  nop
                  b 1f
                  nop
                  nop
                  nop
                1:

                to the new sequence if possible:
                  bne $2, $3, 1f
                  nop
                  j    target
                  nop
                  nop
                  nop
                1:

                OR to the new sequence:
                  bne $2, $3, 1f
                  nop
                  lui $25, target >> 16
                  ori $25, $25, target & 0xffff
                  jr $25
                  nop
                1:

                Note: beq/bne/bc1t are converted to bne/beq/bc1f.
            */

            if (*(insn + 2) == 0x10000003) {
                if ((*insn & 0xfc000000) == 0x10000000) // beq
                    *insn = (*insn & 0x03ff0000) | 0x14000005; // bne
                else if ((*insn & 0xfc000000) == 0x14000000) // bne
                    *insn = (*insn & 0x03ff0000) | 0x10000005; // beq
                else if ((*insn & 0xffff0000) == 0x45010000) // bc1t
                    *insn = 0x45000005; // bc1f
                else
                    ASSERT(0);
            }

            insn = insn + 2;
            if ((reinterpret_cast<intptr_t>(insn) + 4) >> 28
                == reinterpret_cast<intptr_t>(to) >> 28) {
                *insn = 0x08000000 | ((reinterpret_cast<intptr_t>(to) >> 2) & 0x3ffffff);
                *(insn + 1) = 0;
                return 4 * sizeof(MIPSWord);
            }

            intptr_t newTargetAddress = reinterpret_cast<intptr_t>(to);
            /* lui */
            *insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((newTargetAddress >> 16) & 0xffff);
            /* ori */
            *(insn + 1) = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (newTargetAddress & 0xffff);
            /* jr */
            *(insn + 2) = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS);
            return 5 * sizeof(MIPSWord);
        }

        *insn = (*insn & 0xffff0000) | (diff & 0xffff);
        return sizeof(MIPSWord);
    }

    static int linkCallInternal(void* from, void* to)
    {
        MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);
        insn = insn - 4;

        if ((*(insn + 2) & 0xfc000000) == 0x0c000000) { // jal
            if ((reinterpret_cast<intptr_t>(from) - 4) >> 28
                == reinterpret_cast<intptr_t>(to) >> 28) {
                *(insn + 2) = 0x0c000000 | ((reinterpret_cast<intptr_t>(to) >> 2) & 0x3ffffff);
                return sizeof(MIPSWord);
            }

            /* lui $25, (to >> 16) & 0xffff */
            *insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((reinterpret_cast<intptr_t>(to) >> 16) & 0xffff);
            /* ori $25, $25, to & 0xffff */
            *(insn + 1) = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (reinterpret_cast<intptr_t>(to) & 0xffff);
            /* jalr $25 */
            *(insn + 2) = 0x0000f809 | (MIPSRegisters::t9 << OP_SH_RS);
            return 3 * sizeof(MIPSWord);
        }

        ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
        ASSERT((*(insn + 1) & 0xfc000000) == 0x34000000); // ori

        /* lui */
        *insn = (*insn & 0xffff0000) | ((reinterpret_cast<intptr_t>(to) >> 16) & 0xffff);
        /* ori */
        *(insn + 1) = (*(insn + 1) & 0xffff0000) | (reinterpret_cast<intptr_t>(to) & 0xffff);
        return 2 * sizeof(MIPSWord);
    }

    AssemblerBuffer m_buffer;
    Jumps m_jumps;
};

} // namespace JSC

#endif // ENABLE(ASSEMBLER) && CPU(MIPS)

#endif // MIPSAssembler_h

Lines 38-43 namespace JSC { typedef MacroAssemblerAR JavaScriptCore/assembler/MacroAssembler.h_sec1
- JavaScriptCore/assembler/MacroAssembler.h +4 lines
38	#include "MacroAssemblerARM.h"	38	#include "MacroAssemblerARM.h"
39	namespace JSC { typedef MacroAssemblerARM MacroAssemblerBase; };	39	namespace JSC { typedef MacroAssemblerARM MacroAssemblerBase; };
40		40
		41	#elif CPU(MIPS)
		42	#include "MacroAssemblerMIPS.h"
		43	namespace JSC { typedef MacroAssemblerMIPS MacroAssemblerBase; };
		44
41	#elif CPU(X86)	45	#elif CPU(X86)
42	#include "MacroAssemblerX86.h"	46	#include "MacroAssemblerX86.h"
43	namespace JSC { typedef MacroAssemblerX86 MacroAssemblerBase; };	47	namespace JSC { typedef MacroAssemblerX86 MacroAssemblerBase; };



/*
 * Copyright (C) 2008 Apple Inc. All rights reserved.
 * Copyright (C) 2009 MIPS Technologies, Inc. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY MIPS TECHNOLOGIES, INC. ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL MIPS TECHNOLOGIES, INC. OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef MacroAssemblerMIPS_h
#define MacroAssemblerMIPS_h

#include <wtf/Platform.h>

#if ENABLE(ASSEMBLER) && CPU(MIPS)

#include "MIPSAssembler.h"
#include "AbstractMacroAssembler.h"

namespace JSC {

class MacroAssemblerMIPS : public AbstractMacroAssembler<MIPSAssembler> {
public:

    MacroAssemblerMIPS()
        : m_fixedWidth(false)
    {
    }

    static const Scale ScalePtr = TimesFour;

    // For storing immediate number
    static const RegisterID immTempRegister = MIPSRegisters::t0;
    // For storing data loaded from the memory
    static const RegisterID dataTempRegister = MIPSRegisters::t1;
    // For storing address base
    static const RegisterID addrTempRegister = MIPSRegisters::t2;
    // For storing compare result
    static const RegisterID cmpTempRegister = MIPSRegisters::t3;

    // FP temp register
    static const FPRegisterID fpTempRegister = MIPSRegisters::f16;

    enum Condition {
        Equal,
        NotEqual,
        Above,
        AboveOrEqual,
        Below,
        BelowOrEqual,
        GreaterThan,
        GreaterThanOrEqual,
        LessThan,
        LessThanOrEqual,
        Overflow,
        Signed,
        Zero,
        NonZero
    };

    enum DoubleCondition {
        DoubleEqual,
        DoubleNotEqual,
        DoubleGreaterThan,
        DoubleGreaterThanOrEqual,
        DoubleLessThan,
        DoubleLessThanOrEqual,
        DoubleEqualOrUnordered,
        DoubleNotEqualOrUnordered,
        DoubleGreaterThanOrUnordered,
        DoubleGreaterThanOrEqualOrUnordered,
        DoubleLessThanOrUnordered,
        DoubleLessThanOrEqualOrUnordered
    };

    static const RegisterID stackPointerRegister = MIPSRegisters::sp;
    static const RegisterID returnAddressRegister = MIPSRegisters::ra;

    // Integer arithmetic operations:
    //
    // Operations are typically two operand - operation(source, srcDst)
    // For many operations the source may be an Imm32, the srcDst operand
    // may often be a memory location (explictly described using an Address
    // object).

    void add32(RegisterID src, RegisterID dest)
    {
        m_assembler.addu(dest, dest, src);
    }

    void add32(Imm32 imm, RegisterID dest)
    {
        add32(imm, dest, dest);
    }

    void add32(Imm32 imm, RegisterID src, RegisterID dest)
    {
        if (!imm.m_isPointer && imm.m_value >= -32768 && imm.m_value <= 32767
            && !m_fixedWidth) {
            /*
              addiu     dest, src, imm
            */
            m_assembler.addiu(dest, src, imm.m_value);
        } else {
            /*
              li        immTemp, imm
              addu      dest, src, immTemp
            */
            move(imm, immTempRegister);
            m_assembler.addu(dest, src, immTempRegister);
        }
    }

    void add32(Imm32 imm, Address address)
    {
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth) {
            /*
              lw        dataTemp, offset(base)
              li        immTemp, imm
              addu      dataTemp, dataTemp, immTemp
              sw        dataTemp, offset(base)
            */
            m_assembler.lw(dataTempRegister, address.base, address.offset);
            if (!imm.m_isPointer
                && imm.m_value >= -32768 && imm.m_value <= 32767
                && !m_fixedWidth)
                m_assembler.addiu(dataTempRegister, dataTempRegister,
                                  imm.m_value);
            else {
                move(imm, immTempRegister);
                m_assembler.addu(dataTempRegister, dataTempRegister,
                                 immTempRegister);
            }
            m_assembler.sw(dataTempRegister, address.base, address.offset);
        } else {
            /*
              lui       addrTemp, (offset + 0x8000) >> 16
              addu      addrTemp, addrTemp, base
              lw        dataTemp, (offset & 0xffff)(addrTemp)
              li        immtemp, imm
              addu      dataTemp, dataTemp, immTemp
              sw        dataTemp, (offset & 0xffff)(addrTemp)
            */
            m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lw(dataTempRegister, addrTempRegister, address.offset);

            if (imm.m_value >= -32768 && imm.m_value <= 32767 && !m_fixedWidth)
                m_assembler.addiu(dataTempRegister, dataTempRegister,
                                  imm.m_value);
            else {
                move(imm, immTempRegister);
                m_assembler.addu(dataTempRegister, dataTempRegister,
                                 immTempRegister);
            }
            m_assembler.sw(dataTempRegister, addrTempRegister, address.offset);
        }
    }

    void add32(Address src, RegisterID dest)
    {
        load32(src, dataTempRegister);
        add32(dataTempRegister, dest);
    }

    void add32(RegisterID src, Address dest)
    {
        if (dest.offset >= -32768 && dest.offset <= 32767 && !m_fixedWidth) {
            /*
              lw        dataTemp, offset(base)
              addu      dataTemp, dataTemp, src
              sw        dataTemp, offset(base)
            */
            m_assembler.lw(dataTempRegister, dest.base, dest.offset);
            m_assembler.addu(dataTempRegister, dataTempRegister, src);
            m_assembler.sw(dataTempRegister, dest.base, dest.offset);
        } else {
            /*
              lui       addrTemp, (offset + 0x8000) >> 16
              addu      addrTemp, addrTemp, base
              lw        dataTemp, (offset & 0xffff)(addrTemp)
              addu      dataTemp, dataTemp, src
              sw        dataTemp, (offset & 0xffff)(addrTemp)
            */
            m_assembler.lui(addrTempRegister, (dest.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister, dest.base);
            m_assembler.lw(dataTempRegister, addrTempRegister, dest.offset);
            m_assembler.addu(dataTempRegister, dataTempRegister, src);
            m_assembler.sw(dataTempRegister, addrTempRegister, dest.offset);
        }
    }

    void add32(Imm32 imm, AbsoluteAddress address)
    {
        /*
           li   addrTemp, address
           li   immTemp, imm
           lw   dataTemp, 0(addrTemp)
           addu dataTemp, dataTemp, immTemp
           sw   dataTemp, 0(addrTemp)
        */
        move(ImmPtr(address.m_ptr), addrTempRegister);
        m_assembler.lw(dataTempRegister, addrTempRegister, 0);
        if (!imm.m_isPointer && imm.m_value >= -32768 && imm.m_value <= 32767
            && !m_fixedWidth)
            m_assembler.addiu(dataTempRegister, dataTempRegister, imm.m_value);
        else {
            move(imm, immTempRegister);
            m_assembler.addu(dataTempRegister, dataTempRegister, immTempRegister);
        }
        m_assembler.sw(dataTempRegister, addrTempRegister, 0);
    }

    void and32(RegisterID src, RegisterID dest)
    {
        m_assembler.andInsn(dest, dest, src);
    }

    void and32(Imm32 imm, RegisterID dest)
    {
        if (!imm.m_isPointer && !imm.m_value && !m_fixedWidth)
            move(MIPSRegisters::zero, dest);
        else if (!imm.m_isPointer && imm.m_value > 0 && imm.m_value < 65535
                 && !m_fixedWidth)
            m_assembler.andi(dest, dest, imm.m_value);
        else {
            /*
              li        immTemp, imm
              and       dest, dest, immTemp
            */
            move(imm, immTempRegister);
            m_assembler.andInsn(dest, dest, immTempRegister);
        }
    }

    void lshift32(Imm32 imm, RegisterID dest)
    {
        m_assembler.sll(dest, dest, imm.m_value);
    }

    void lshift32(RegisterID shiftAmount, RegisterID dest)
    {
        m_assembler.sllv(dest, dest, shiftAmount);
    }

    void mul32(RegisterID src, RegisterID dest)
    {
        m_assembler.mul(dest, dest, src);
    }

    void mul32(Imm32 imm, RegisterID src, RegisterID dest)
    {
        if (!imm.m_isPointer && !imm.m_value && !m_fixedWidth)
            move(MIPSRegisters::zero, dest);
        else if (!imm.m_isPointer && imm.m_value == 1 && !m_fixedWidth)
            move(src, dest);
        else {
            /*
                li      dataTemp, imm
                mul     dest, src, dataTemp
            */
            move(imm, dataTempRegister);
            m_assembler.mul(dest, src, dataTempRegister);
        }
    }

    void not32(RegisterID srcDest)
    {
        m_assembler.nor(srcDest, srcDest, MIPSRegisters::zero);
    }

    void or32(RegisterID src, RegisterID dest)
    {
        m_assembler.orInsn(dest, dest, src);
    }

    void or32(Imm32 imm, RegisterID dest)
    {
        if (!imm.m_isPointer && !imm.m_value && !m_fixedWidth)
            return;

        if (!imm.m_isPointer && imm.m_value > 0 && imm.m_value < 65535
            && !m_fixedWidth) {
            m_assembler.ori(dest, dest, imm.m_value);
            return;
        }

        /*
            li      dataTemp, imm
            or      dest, dest, dataTemp
        */
        move(imm, dataTempRegister);
        m_assembler.orInsn(dest, dest, dataTempRegister);
    }

    void rshift32(RegisterID shiftAmount, RegisterID dest)
    {
        m_assembler.srav(dest, dest, shiftAmount);
    }

    void rshift32(Imm32 imm, RegisterID dest)
    {
        m_assembler.sra(dest, dest, imm.m_value);
    }

    void sub32(RegisterID src, RegisterID dest)
    {
        m_assembler.subu(dest, dest, src);
    }

    void sub32(Imm32 imm, RegisterID dest)
    {
        if (!imm.m_isPointer && imm.m_value >= -32767 && imm.m_value <= 32768
            && !m_fixedWidth) {
            /*
              addiu     dest, src, imm
            */
            m_assembler.addiu(dest, dest, -imm.m_value);
        } else {
            /*
              li        immTemp, imm
              subu      dest, src, immTemp
            */
            move(imm, immTempRegister);
            m_assembler.subu(dest, dest, immTempRegister);
        }
    }

    void sub32(Imm32 imm, Address address)
    {
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth) {
            /*
              lw        dataTemp, offset(base)
              li        immTemp, imm
              subu      dataTemp, dataTemp, immTemp
              sw        dataTemp, offset(base)
            */
            m_assembler.lw(dataTempRegister, address.base, address.offset);
            if (!imm.m_isPointer
                && imm.m_value >= -32767 && imm.m_value <= 32768
                && !m_fixedWidth)
                m_assembler.addiu(dataTempRegister, dataTempRegister,
                                  -imm.m_value);
            else {
                move(imm, immTempRegister);
                m_assembler.subu(dataTempRegister, dataTempRegister,
                                 immTempRegister);
            }
            m_assembler.sw(dataTempRegister, address.base, address.offset);
        } else {
            /*
              lui       addrTemp, (offset + 0x8000) >> 16
              addu      addrTemp, addrTemp, base
              lw        dataTemp, (offset & 0xffff)(addrTemp)
              li        immtemp, imm
              subu      dataTemp, dataTemp, immTemp
              sw        dataTemp, (offset & 0xffff)(addrTemp)
            */
            m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lw(dataTempRegister, addrTempRegister, address.offset);

            if (!imm.m_isPointer
                && imm.m_value >= -32767 && imm.m_value <= 32768
                && !m_fixedWidth)
                m_assembler.addiu(dataTempRegister, dataTempRegister,
                                  -imm.m_value);
            else {
                move(imm, immTempRegister);
                m_assembler.subu(dataTempRegister, dataTempRegister,
                                 immTempRegister);
            }
            m_assembler.sw(dataTempRegister, addrTempRegister, address.offset);
        }
    }

    void sub32(Address src, RegisterID dest)
    {
        load32(src, dataTempRegister);
        sub32(dataTempRegister, dest);
    }

    void sub32(Imm32 imm, AbsoluteAddress address)
    {
        /*
           li   addrTemp, address
           li   immTemp, imm
           lw   dataTemp, 0(addrTemp)
           subu dataTemp, dataTemp, immTemp
           sw   dataTemp, 0(addrTemp)
        */
        move(ImmPtr(address.m_ptr), addrTempRegister);
        m_assembler.lw(dataTempRegister, addrTempRegister, 0);

        if (!imm.m_isPointer && imm.m_value >= -32767 && imm.m_value <= 32768
            && !m_fixedWidth) {
            m_assembler.addiu(dataTempRegister, dataTempRegister,
                              -imm.m_value);
        } else {
            move(imm, immTempRegister);
            m_assembler.subu(dataTempRegister, dataTempRegister, immTempRegister);
        }
        m_assembler.sw(dataTempRegister, addrTempRegister, 0);
    }

    void xor32(RegisterID src, RegisterID dest)
    {
        m_assembler.xorInsn(dest, dest, src);
    }

    void xor32(Imm32 imm, RegisterID dest)
    {
        /*
            li  immTemp, imm
            xor dest, dest, immTemp
        */
        move(imm, immTempRegister);
        m_assembler.xorInsn(dest, dest, immTempRegister);
    }

    // Memory access operations:
    //
    // Loads are of the form load(address, destination) and stores of the form
    // store(source, address).  The source for a store may be an Imm32.  Address
    // operand objects to loads and store will be implicitly constructed if a
    // register is passed.

    void load32(ImplicitAddress address, RegisterID dest)
    {
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth)
            m_assembler.lw(dest, address.base, address.offset);
        else {
            /*
                lui     addrTemp, (offset + 0x8000) >> 16
                addu    addrTemp, addrTemp, base
                lw      dest, (offset & 0xffff)(addrTemp)
              */
            m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lw(dest, addrTempRegister, address.offset);
        }
    }

    void load32(BaseIndex address, RegisterID dest)
    {
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth) {
            /*
                sll     addrTemp, address.index, address.scale
                addu    addrTemp, addrTemp, address.base
                lw      dest, address.offset(addrTemp)
            */
            m_assembler.sll(addrTempRegister, address.index, address.scale);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lw(dest, addrTempRegister, address.offset);
        } else {
            /*
                sll     addrTemp, address.index, address.scale
                addu    addrTemp, addrTemp, address.base
                lui     immTemp, (address.offset + 0x8000) >> 16
                addu    addrTemp, addrTemp, immTemp
                lw      dest, (address.offset & 0xffff)(at)
            */
            m_assembler.sll(addrTempRegister, address.index, address.scale);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lui(immTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister,
                             immTempRegister);
            m_assembler.lw(dest, addrTempRegister, address.offset);
        }
    }

    void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
    {
        if (address.offset >= -32768 && address.offset <= 32764
            && !m_fixedWidth) {
            /*
                sll     addrTemp, address.index, address.scale
                addu    addrTemp, addrTemp, address.base
                (Big-Endian)
                lwl     dest, address.offset(addrTemp)
                lwr     dest, address.offset+3(addrTemp)
                (Little-Endian)
                lwl     dest, address.offset+3(addrTemp)
                lwr     dest, address.offset(addrTemp)
            */
            m_assembler.sll(addrTempRegister, address.index, address.scale);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
#if CPU(BIG_ENDIAN)
            m_assembler.lwl(dest, addrTempRegister, address.offset);
            m_assembler.lwr(dest, addrTempRegister, address.offset + 3);
#else
            m_assembler.lwl(dest, addrTempRegister, address.offset + 3);
            m_assembler.lwr(dest, addrTempRegister, address.offset);

#endif
        } else {
            /*
                sll     addrTemp, address.index, address.scale
                addu    addrTemp, addrTemp, address.base
                lui     immTemp, address.offset >> 16
                ori     immTemp, immTemp, address.offset & 0xffff
                addu    addrTemp, addrTemp, immTemp
                (Big-Endian)
                lw      dest, 0(at)
                lw      dest, 3(at)
                (Little-Endian)
                lw      dest, 3(at)
                lw      dest, 0(at)
            */
            m_assembler.sll(addrTempRegister, address.index, address.scale);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lui(immTempRegister, address.offset >> 16);
            m_assembler.ori(immTempRegister, immTempRegister, address.offset);
            m_assembler.addu(addrTempRegister, addrTempRegister,
                             immTempRegister);
#if CPU(BIG_ENDIAN)
            m_assembler.lwl(dest, addrTempRegister, 0);
            m_assembler.lwr(dest, addrTempRegister, 3);
#else
            m_assembler.lwl(dest, addrTempRegister, 3);
            m_assembler.lwr(dest, addrTempRegister, 0);
#endif
        }
    }

    void load32(void* address, RegisterID dest)
    {
        /*
            li  addrTemp, address
            lw  dest, 0(addrTemp)
        */
        move(ImmPtr(address), addrTempRegister);
        m_assembler.lw(dest, addrTempRegister, 0);
    }

    DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
    {
        m_fixedWidth = true;
        /*
            lui addrTemp, address.offset >> 16
            ori addrTemp, addrTemp, address.offset & 0xffff
            addu        addrTemp, addrTemp, address.base
            lw  dest, 0(addrTemp)
        */
        DataLabel32 dataLabel(this);
        move(Imm32(address.offset), addrTempRegister);
        m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
        m_assembler.lw(dest, addrTempRegister, 0);
        m_fixedWidth = false;
        return dataLabel;
    }

    Label loadPtrWithPatchToLEA(Address address, RegisterID dest)
    {
        m_fixedWidth = true;
        /*
            lui         addrTemp, address.offset >> 16
            ori         addrTemp, addrTemp, address.offset & 0xffff
            addu        addrTemp, addrTemp, address.base
            lw          dest, 0(addrTemp)
        */
        Label label(this);
        move(Imm32(address.offset), addrTempRegister);
        m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
        m_assembler.lw(dest, addrTempRegister, 0);
        m_fixedWidth = false;
        return label;
    }

    Label loadPtrWithAddressOffsetPatch(Address address, RegisterID dest)
    {
        return loadPtrWithPatchToLEA(address, dest);
    }

    /* Need to use zero-extened load half-word for load16.  */
    void load16(BaseIndex address, RegisterID dest)
    {
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth) {
            /*
                sll     addrTemp, address.index, address.scale
                addu    addrTemp, addrTemp, address.base
                lhu     dest, address.offset(addrTemp)
            */
            m_assembler.sll(addrTempRegister, address.index, address.scale);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lhu(dest, addrTempRegister, address.offset);
        } else {
            /*
                sll     addrTemp, address.index, address.scale
                addu    addrTemp, addrTemp, address.base
                lui     immTemp, (address.offset + 0x8000) >> 16
                addu    addrTemp, addrTemp, immTemp
                lhu     dest, (address.offset & 0xffff)(addrTemp)
            */
            m_assembler.sll(addrTempRegister, address.index, address.scale);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lui(immTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister,
                             immTempRegister);
            m_assembler.lhu(dest, addrTempRegister, address.offset);
        }
    }

    DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
    {
        m_fixedWidth = true;
        /*
            lui addrTemp, address.offset >> 16
            ori addrTemp, addrTemp, address.offset & 0xffff
            addu        addrTemp, addrTemp, address.base
            sw  src, 0(addrTemp)
        */
        DataLabel32 dataLabel(this);
        move(Imm32(address.offset), addrTempRegister);
        m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
        m_assembler.sw(src, addrTempRegister, 0);
        m_fixedWidth = false;
        return dataLabel;
    }

    void store32(RegisterID src, ImplicitAddress address)
    {
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth)
            m_assembler.sw(src, address.base, address.offset);
        else {
            /*
                lui     addrTemp, (offset + 0x8000) >> 16
                addu    addrTemp, addrTemp, base
                sw      src, (offset & 0xffff)(addrTemp)
              */
            m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.sw(src, addrTempRegister, address.offset);
        }
    }

    void store32(RegisterID src, BaseIndex address)
    {
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth) {
            /*
                sll     addrTemp, address.index, address.scale
                addu    addrTemp, addrTemp, address.base
                sw      src, address.offset(addrTemp)
            */
            m_assembler.sll(addrTempRegister, address.index, address.scale);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.sw(src, addrTempRegister, address.offset);
        } else {
            /*
                sll     addrTemp, address.index, address.scale
                addu    addrTemp, addrTemp, address.base
                lui     immTemp, (address.offset + 0x8000) >> 16
                addu    addrTemp, addrTemp, immTemp
                sw      src, (address.offset & 0xffff)(at)
            */
            m_assembler.sll(addrTempRegister, address.index, address.scale);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.lui(immTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister,
                             immTempRegister);
            m_assembler.sw(src, addrTempRegister, address.offset);
        }
    }

    void store32(Imm32 imm, ImplicitAddress address)
    {
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth) {
            if (!imm.m_isPointer && !imm.m_value)
                m_assembler.sw(MIPSRegisters::zero, address.base,
                               address.offset);
            else {
                move(imm, immTempRegister);
                m_assembler.sw(immTempRegister, address.base, address.offset);
            }
        } else {
            /*
                lui     addrTemp, (offset + 0x8000) >> 16
                addu    addrTemp, addrTemp, base
                sw      immTemp, (offset & 0xffff)(addrTemp)
              */
            m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            if (!imm.m_isPointer && !imm.m_value && !m_fixedWidth)
                m_assembler.sw(MIPSRegisters::zero, addrTempRegister,
                               address.offset);
            else {
                move(imm, immTempRegister);
                m_assembler.sw(immTempRegister, addrTempRegister,
                               address.offset);
            }
        }
    }

    void store32(RegisterID src, void* address)
    {
        /*
            li  addrTemp, address
            sw  src, 0(addrTemp)
        */
        move(ImmPtr(address), addrTempRegister);
        m_assembler.sw(src, addrTempRegister, 0);
    }

    void store32(Imm32 imm, void* address)
    {
        /*
            li  immTemp, imm
            li  addrTemp, address
            sw  src, 0(addrTemp)
        */
        if (!imm.m_isPointer && !imm.m_value && !m_fixedWidth) {
            move(ImmPtr(address), addrTempRegister);
            m_assembler.sw(MIPSRegisters::zero, addrTempRegister, 0);
        } else {
            move(imm, immTempRegister);
            move(ImmPtr(address), addrTempRegister);
            m_assembler.sw(immTempRegister, addrTempRegister, 0);
        }
    }

    // Floating-point operations:

    bool supportsFloatingPoint() const
    {
#if WTF_MIPS_DOUBLE_FLOAT
        return true;
#else
        return false;
#endif
    }

    bool supportsFloatingPointTruncate() const
    {
#if WTF_MIPS_DOUBLE_FLOAT && WTF_MIPS_ISA_AT_LEAST(2)
        return true;
#else
        return false;
#endif
    }

    // Stack manipulation operations:
    //
    // The ABI is assumed to provide a stack abstraction to memory,
    // containing machine word sized units of data.  Push and pop
    // operations add and remove a single register sized unit of data
    // to or from the stack.  Peek and poke operations read or write
    // values on the stack, without moving the current stack position.

    void pop(RegisterID dest)
    {
        m_assembler.lw(dest, MIPSRegisters::sp, 0);
        m_assembler.addiu(MIPSRegisters::sp, MIPSRegisters::sp, 4);
    }

    void push(RegisterID src)
    {
        m_assembler.addiu(MIPSRegisters::sp, MIPSRegisters::sp, -4);
        m_assembler.sw(src, MIPSRegisters::sp, 0);
    }

    void push(Address address)
    {
        load32(address, dataTempRegister);
        push(dataTempRegister);
    }

    void push(Imm32 imm)
    {
        move(imm, immTempRegister);
        push(immTempRegister);
    }

    // Register move operations:
    //
    // Move values in registers.

    void move(Imm32 imm, RegisterID dest)
    {
        if (!imm.m_isPointer && !imm.m_value && !m_fixedWidth)
            move(MIPSRegisters::zero, dest);
        else if (imm.m_isPointer || m_fixedWidth) {
            m_assembler.lui(dest, imm.m_value >> 16);
            m_assembler.ori(dest, dest, imm.m_value);
        } else
            m_assembler.li(dest, imm.m_value);
    }

    void move(RegisterID src, RegisterID dest)
    {
        if (src != dest || m_fixedWidth)
            m_assembler.move(dest, src);
    }

    void move(ImmPtr imm, RegisterID dest)
    {
        move(Imm32(imm), dest);
    }

    void swap(RegisterID reg1, RegisterID reg2)
    {
        move(reg1, immTempRegister);
        move(reg2, reg1);
        move(immTempRegister, reg2);
    }

    void signExtend32ToPtr(RegisterID src, RegisterID dest)
    {
        if (src != dest || m_fixedWidth)
            move(src, dest);
    }

    void zeroExtend32ToPtr(RegisterID src, RegisterID dest)
    {
        if (src != dest || m_fixedWidth)
            move(src, dest);
    }

    // Forwards / external control flow operations:
    //
    // This set of jump and conditional branch operations return a Jump
    // object which may linked at a later point, allow forwards jump,
    // or jumps that will require external linkage (after the code has been
    // relocated).
    //
    // For branches, signed <, >, <= and >= are denoted as l, g, le, and ge
    // respecitvely, for unsigned comparisons the names b, a, be, and ae are
    // used (representing the names 'below' and 'above').
    //
    // Operands to the comparision are provided in the expected order, e.g.
    // jle32(reg1, Imm32(5)) will branch if the value held in reg1, when
    // treated as a signed 32bit value, is less than or equal to 5.
    //
    // jz and jnz test whether the first operand is equal to zero, and take
    // an optional second operand of a mask under which to perform the test.

    Jump branch32(Condition cond, RegisterID left, RegisterID right)
    {
        if (cond == Equal || cond == Zero)
            return branchEqual(left, right);
        if (cond == NotEqual || cond == NonZero)
            return branchNotEqual(left, right);
        if (cond == Above) {
            m_assembler.sltu(cmpTempRegister, right, left);
            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == AboveOrEqual) {
            m_assembler.sltu(cmpTempRegister, left, right);
            return branchEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == Below) {
            m_assembler.sltu(cmpTempRegister, left, right);
            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == BelowOrEqual) {
            m_assembler.sltu(cmpTempRegister, right, left);
            return branchEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == GreaterThan) {
            m_assembler.slt(cmpTempRegister, right, left);
            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == GreaterThanOrEqual) {
            m_assembler.slt(cmpTempRegister, left, right);
            return branchEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == LessThan) {
            m_assembler.slt(cmpTempRegister, left, right);
            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == LessThanOrEqual) {
            m_assembler.slt(cmpTempRegister, right, left);
            return branchEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == Overflow) {
            /*
                xor     cmpTemp, left, right
                bgez    No_overflow, cmpTemp    # same sign bit -> no overflow
                nop
                subu    cmpTemp, left, right
                xor     cmpTemp, cmpTemp, left
                bgez    No_overflow, cmpTemp    # same sign bit -> no overflow
                nop
                b       Overflow
                nop
                nop
                nop
                nop
                nop
              No_overflow:
            */
            m_assembler.xorInsn(cmpTempRegister, left, right);
            m_assembler.bgez(cmpTempRegister, 11);
            m_assembler.nop();
            m_assembler.subu(cmpTempRegister, left, right);
            m_assembler.xorInsn(cmpTempRegister, cmpTempRegister, left);
            m_assembler.bgez(cmpTempRegister, 7);
            m_assembler.nop();
            return jump();
        }
        if (cond == Signed) {
            m_assembler.subu(cmpTempRegister, left, right);
            // Check if the result is negative.
            m_assembler.slt(cmpTempRegister, cmpTempRegister,
                            MIPSRegisters::zero);
            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        ASSERT(0);

        return Jump();
    }

    Jump branch32(Condition cond, RegisterID left, Imm32 right)
    {
        move(right, immTempRegister);
        return branch32(cond, left, immTempRegister);
    }

    Jump branch32(Condition cond, RegisterID left, Address right)
    {
        load32(right, dataTempRegister);
        return branch32(cond, left, dataTempRegister);
    }

    Jump branch32(Condition cond, Address left, RegisterID right)
    {
        load32(left, dataTempRegister);
        return branch32(cond, dataTempRegister, right);
    }

    Jump branch32(Condition cond, Address left, Imm32 right)
    {
        load32(left, dataTempRegister);
        move(right, immTempRegister);
        return branch32(cond, dataTempRegister, immTempRegister);
    }

    Jump branch32(Condition cond, BaseIndex left, Imm32 right)
    {
        load32(left, dataTempRegister);
        // Be careful that the previous load32() uses immTempRegister.
        // So, we need to put move() after load32().
        move(right, immTempRegister);
        return branch32(cond, dataTempRegister, immTempRegister);
    }

    Jump branch32WithUnalignedHalfWords(Condition cond, BaseIndex left, Imm32 right)
    {
        load32WithUnalignedHalfWords(left, dataTempRegister);
        // Be careful that the previous load32WithUnalignedHalfWords()
        // uses immTempRegister.
        // So, we need to put move() after load32WithUnalignedHalfWords().
        move(right, immTempRegister);
        return branch32(cond, dataTempRegister, immTempRegister);
    }

    Jump branch32(Condition cond, AbsoluteAddress left, RegisterID right)
    {
        load32(left.m_ptr, dataTempRegister);
        return branch32(cond, dataTempRegister, right);
    }

    Jump branch32(Condition cond, AbsoluteAddress left, Imm32 right)
    {
        load32(left.m_ptr, dataTempRegister);
        move(right, immTempRegister);
        return branch32(cond, dataTempRegister, immTempRegister);
    }

    Jump branch16(Condition cond, BaseIndex left, RegisterID right)
    {
        load16(left, dataTempRegister);
        return branch32(cond, dataTempRegister, right);
    }

    Jump branch16(Condition cond, BaseIndex left, Imm32 right)
    {
        ASSERT(!(right.m_value & 0xFFFF0000));
        load16(left, dataTempRegister);
        // Be careful that the previous load16() uses immTempRegister.
        // So, we need to put move() after load16().
        move(right, immTempRegister);
        return branch32(cond, dataTempRegister, immTempRegister);
    }

    Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask)
    {
        ASSERT((cond == Zero) || (cond == NonZero));
        m_assembler.andInsn(cmpTempRegister, reg, mask);
        if (cond == Zero)
            return branchEqual(cmpTempRegister, MIPSRegisters::zero);
        return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
    }

    Jump branchTest32(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1))
    {
        ASSERT((cond == Zero) || (cond == NonZero));
        if (mask.m_value == -1 && !m_fixedWidth) {
            if (cond == Zero)
                return branchEqual(reg, MIPSRegisters::zero);
            return branchNotEqual(reg, MIPSRegisters::zero);
        }
        move(mask, immTempRegister);
        return branchTest32(cond, reg, immTempRegister);
    }

    Jump branchTest32(Condition cond, Address address, Imm32 mask = Imm32(-1))
    {
        load32(address, dataTempRegister);
        return branchTest32(cond, dataTempRegister, mask);
    }

    Jump branchTest32(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1))
    {
        load32(address, dataTempRegister);
        return branchTest32(cond, dataTempRegister, mask);
    }

    Jump jump()
    {
        return branchEqual(MIPSRegisters::zero, MIPSRegisters::zero);
    }

    void jump(RegisterID target)
    {
        m_assembler.jr(target);
        m_assembler.nop();
    }

    void jump(Address address)
    {
        m_fixedWidth = true;
        load32(address, MIPSRegisters::t9);
        m_assembler.jr(MIPSRegisters::t9);
        m_assembler.nop();
        m_fixedWidth = false;
    }

    // Arithmetic control flow operations:
    //
    // This set of conditional branch operations branch based
    // on the result of an arithmetic operation.  The operation
    // is performed as normal, storing the result.
    //
    // * jz operations branch if the result is zero.
    // * jo operations branch if the (signed) arithmetic
    //   operation caused an overflow to occur.

    Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest)
    {
        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
        if (cond == Overflow) {
            /*
                move    dest, dataTemp
                xor     cmpTemp, dataTemp, src
                bltz    cmpTemp, No_overflow    # diff sign bit -> no overflow
                addu    dest, dataTemp, src
                xor     cmpTemp, dest, dataTemp
                bgez    cmpTemp, No_overflow    # same sign big -> no overflow
                nop
                b       Overflow
                nop
                nop
                nop
                nop
                nop
            No_overflow:
            */
            move(dest, dataTempRegister);
            m_assembler.xorInsn(cmpTempRegister, dataTempRegister, src);
            m_assembler.bltz(cmpTempRegister, 10);
            m_assembler.addu(dest, dataTempRegister, src);
            m_assembler.xorInsn(cmpTempRegister, dest, dataTempRegister);
            m_assembler.bgez(cmpTempRegister, 7);
            m_assembler.nop();
            return jump();
        }
        if (cond == Signed) {
            add32(src, dest);
            // Check if dest is negative.
            m_assembler.slt(cmpTempRegister, dest, MIPSRegisters::zero);
            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == Zero) {
            add32(src, dest);
            return branchEqual(dest, MIPSRegisters::zero);
        }
        if (cond == NonZero) {
            add32(src, dest);
            return branchNotEqual(dest, MIPSRegisters::zero);
        }
        ASSERT(0);
        return Jump();
    }

    Jump branchAdd32(Condition cond, Imm32 imm, RegisterID dest)
    {
        move(imm, immTempRegister);
        return branchAdd32(cond, immTempRegister, dest);
    }

    Jump branchMul32(Condition cond, RegisterID src, RegisterID dest)
    {
        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
        if (cond == Overflow) {
            /*
                mult    src, dest
                mfhi    dataTemp
                mflo    dest
                sra     addrTemp, dest, 31
                beq     dataTemp, addrTemp, No_overflow # all sign bits (bit 63 to bit 31) are the same -> no overflow
                nop
                b       Overflow
                nop
                nop
                nop
                nop
                nop
            No_overflow:
            */
            m_assembler.mult(src, dest);
            m_assembler.mfhi(dataTempRegister);
            m_assembler.mflo(dest);
            m_assembler.sra(addrTempRegister, dest, 31);
            m_assembler.beq(dataTempRegister, addrTempRegister, 7);
            m_assembler.nop();
            return jump();
        }
        if (cond == Signed) {
            mul32(src, dest);
            // Check if dest is negative.
            m_assembler.slt(cmpTempRegister, dest, MIPSRegisters::zero);
            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == Zero) {
            mul32(src, dest);
            return branchEqual(dest, MIPSRegisters::zero);
        }
        if (cond == NonZero) {
            mul32(src, dest);
            return branchNotEqual(dest, MIPSRegisters::zero);
        }
        ASSERT(0);
        return Jump();
    }

    Jump branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest)
    {
        move(imm, immTempRegister);
        move(src, dest);
        return branchMul32(cond, immTempRegister, dest);
    }

    Jump branchSub32(Condition cond, RegisterID src, RegisterID dest)
    {
        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
        if (cond == Overflow) {
            /*
                move    dest, dataTemp
                xor     cmpTemp, dataTemp, src
                bgez    cmpTemp, No_overflow    # same sign bit -> no overflow
                subu    dest, dataTemp, src
                xor     cmpTemp, dest, dataTemp
                bgez    cmpTemp, No_overflow    # same sign bit -> no overflow
                nop
                b       Overflow
                nop
                nop
                nop
                nop
                nop
            No_overflow:
            */
            move(dest, dataTempRegister);
            m_assembler.xorInsn(cmpTempRegister, dataTempRegister, src);
            m_assembler.bgez(cmpTempRegister, 10);
            m_assembler.subu(dest, dataTempRegister, src);
            m_assembler.xorInsn(cmpTempRegister, dest, dataTempRegister);
            m_assembler.bgez(cmpTempRegister, 7);
            m_assembler.nop();
            return jump();
        }
        if (cond == Signed) {
            sub32(src, dest);
            // Check if dest is negative.
            m_assembler.slt(cmpTempRegister, dest, MIPSRegisters::zero);
            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
        }
        if (cond == Zero) {
            sub32(src, dest);
            return branchEqual(dest, MIPSRegisters::zero);
        }
        if (cond == NonZero) {
            sub32(src, dest);
            return branchNotEqual(dest, MIPSRegisters::zero);
        }
        ASSERT(0);
        return Jump();
    }

    Jump branchSub32(Condition cond, Imm32 imm, RegisterID dest)
    {
        move(imm, immTempRegister);
        return branchSub32(cond, immTempRegister, dest);
    }

    // Miscellaneous operations:

    void breakpoint()
    {
        m_assembler.bkpt();
    }

    Call nearCall()
    {
        /* We need two words for relaxation.  */
        m_assembler.nop();
        m_assembler.nop();
        m_assembler.jal();
        m_assembler.nop();
        return Call(m_assembler.newJmpSrc(), Call::LinkableNear);
    }

    Call call()
    {
        m_assembler.lui(MIPSRegisters::t9, 0);
        m_assembler.ori(MIPSRegisters::t9, MIPSRegisters::t9, 0);
        m_assembler.jalr(MIPSRegisters::t9);
        m_assembler.nop();
        return Call(m_assembler.newJmpSrc(), Call::Linkable);
    }

    Call call(RegisterID target)
    {
        m_assembler.jalr(target);
        m_assembler.nop();
        return Call(m_assembler.newJmpSrc(), Call::None);
    }

    Call call(Address address)
    {
        m_fixedWidth = true;
        load32(address, MIPSRegisters::t9);
        m_assembler.jalr(MIPSRegisters::t9);
        m_assembler.nop();
        m_fixedWidth = false;
        return Call(m_assembler.newJmpSrc(), Call::None);
    }

    void ret()
    {
        m_assembler.jr(MIPSRegisters::ra);
        m_assembler.nop();
    }

    void set32(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
    {
        if (cond == Equal || cond == Zero) {
            m_assembler.xorInsn(dest, left, right);
            m_assembler.sltiu(dest, dest, 1);
        } else if (cond == NotEqual || cond == NonZero) {
            m_assembler.xorInsn(dest, left, right);
            m_assembler.sltu(dest, MIPSRegisters::zero, dest);
        } else if (cond == Above)
            m_assembler.sltu(dest, right, left);
        else if (cond == AboveOrEqual) {
            m_assembler.sltu(dest, left, right);
            m_assembler.xori(dest, dest, 1);
        } else if (cond == Below)
            m_assembler.sltu(dest, left, right);
        else if (cond == BelowOrEqual) {
            m_assembler.sltu(dest, right, left);
            m_assembler.xori(dest, dest, 1);
        } else if (cond == GreaterThan)
            m_assembler.slt(dest, right, left);
        else if (cond == GreaterThanOrEqual) {
            m_assembler.slt(dest, left, right);
            m_assembler.xori(dest, dest, 1);
        } else if (cond == LessThan)
            m_assembler.slt(dest, left, right);
        else if (cond == LessThanOrEqual) {
            m_assembler.slt(dest, right, left);
            m_assembler.xori(dest, dest, 1);
        } else if (cond == Overflow) {
            /*
                xor     cmpTemp, left, right
                bgez    Done, cmpTemp   # same sign bit -> no overflow
                move    dest, 0
                subu    cmpTemp, left, right
                xor     cmpTemp, cmpTemp, left # diff sign bit -> overflow
                slt     dest, cmpTemp, 0
              Done:
            */
            m_assembler.xorInsn(cmpTempRegister, left, right);
            m_assembler.bgez(cmpTempRegister, 4);
            m_assembler.move(dest, MIPSRegisters::zero);
            m_assembler.subu(cmpTempRegister, left, right);
            m_assembler.xorInsn(cmpTempRegister, cmpTempRegister, left);
            m_assembler.slt(dest, cmpTempRegister, MIPSRegisters::zero);
        } else if (cond == Signed) {
            m_assembler.subu(dest, left, right);
            // Check if the result is negative.
            m_assembler.slt(dest, dest, MIPSRegisters::zero);
        }
    }

    void set32(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
    {
        move(right, immTempRegister);
        set32(cond, left, immTempRegister, dest);
    }

    void setTest32(Condition cond, Address address, Imm32 mask, RegisterID dest)
    {
        ASSERT((cond == Zero) || (cond == NonZero));
        load32(address, dataTempRegister);
        if (mask.m_value == -1 && !m_fixedWidth) {
            if (cond == Zero)
                m_assembler.sltiu(dest, dataTempRegister, 1);
            else
                m_assembler.sltu(dest, MIPSRegisters::zero, dataTempRegister);
        } else {
            move(mask, immTempRegister);
            m_assembler.andInsn(cmpTempRegister, dataTempRegister,
                                 immTempRegister);
            if (cond == Zero)
                m_assembler.sltiu(dest, cmpTempRegister, 1);
            else
                m_assembler.sltu(dest, MIPSRegisters::zero, cmpTempRegister);
        }
    }

    DataLabel32 moveWithPatch(Imm32 imm, RegisterID dest)
    {
        m_fixedWidth = true;
        DataLabel32 label(this);
        move(imm, dest);
        m_fixedWidth = false;
        return label;
    }

    DataLabelPtr moveWithPatch(ImmPtr initialValue, RegisterID dest)
    {
        m_fixedWidth = true;
        DataLabelPtr label(this);
        move(initialValue, dest);
        m_fixedWidth = false;
        return label;
    }

    Jump branchPtrWithPatch(Condition cond, RegisterID left, DataLabelPtr& dataLabel, ImmPtr initialRightValue = ImmPtr(0))
    {
        m_fixedWidth = true;
        dataLabel = moveWithPatch(initialRightValue, immTempRegister);
        Jump temp = branch32(cond, left, immTempRegister);
        m_fixedWidth = false;
        return temp;
    }

    Jump branchPtrWithPatch(Condition cond, Address left, DataLabelPtr& dataLabel, ImmPtr initialRightValue = ImmPtr(0))
    {
        m_fixedWidth = true;
        load32(left, dataTempRegister);
        dataLabel = moveWithPatch(initialRightValue, immTempRegister);
        Jump temp = branch32(cond, dataTempRegister, immTempRegister);
        m_fixedWidth = false;
        return temp;
    }

    DataLabelPtr storePtrWithPatch(ImmPtr initialValue, ImplicitAddress address)
    {
        m_fixedWidth = true;
        DataLabelPtr dataLabel = moveWithPatch(initialValue, dataTempRegister);
        store32(dataTempRegister, address);
        m_fixedWidth = false;
        return dataLabel;
    }

    DataLabelPtr storePtrWithPatch(ImplicitAddress address)
    {
        return storePtrWithPatch(ImmPtr(0), address);
    }

    Call tailRecursiveCall()
    {
        // Like a normal call, but don't update the returned address register
        m_fixedWidth = true;
        move(Imm32(0), MIPSRegisters::t9);
        m_assembler.jr(MIPSRegisters::t9);
        m_assembler.nop();
        m_fixedWidth = false;
        return Call(m_assembler.newJmpSrc(), Call::Linkable);
    }

    Call makeTailRecursiveCall(Jump oldJump)
    {
        oldJump.link(this);
        return tailRecursiveCall();
    }

    void loadDouble(ImplicitAddress address, FPRegisterID dest)
    {
#if WTF_MIPS_ISA(1)
        /*
            li          addrTemp, address.offset
            addu        addrTemp, addrTemp, base
            lwc1        dest, 0(addrTemp)
            lwc1        dest+1, 4(addrTemp)
         */
        move(Imm32(address.offset), addrTempRegister);
        m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
        m_assembler.lwc1(dest, addrTempRegister, 0);
        m_assembler.lwc1(FPRegisterID(dest + 1), addrTempRegister, 4);
#else
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth) {
            m_assembler.ldc1(dest, address.base, address.offset);
        } else {
            /*
                lui     addrTemp, (offset + 0x8000) >> 16
                addu    addrTemp, addrTemp, base
                ldc1    dest, (offset & 0xffff)(addrTemp)
              */
            m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.ldc1(dest, addrTempRegister, address.offset);
        }
#endif
    }

    void storeDouble(FPRegisterID src, ImplicitAddress address)
    {
#if WTF_MIPS_ISA(1)
        /*
            li          addrTemp, address.offset
            addu        addrTemp, addrTemp, base
            swc1        dest, 0(addrTemp)
            swc1        dest+1, 4(addrTemp)
         */
        move(Imm32(address.offset), addrTempRegister);
        m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
        m_assembler.swc1(src, addrTempRegister, 0);
        m_assembler.swc1(FPRegisterID(src + 1), addrTempRegister, 4);
#else
        if (address.offset >= -32768 && address.offset <= 32767
            && !m_fixedWidth)
            m_assembler.sdc1(src, address.base, address.offset);
        else {
            /*
                lui     addrTemp, (offset + 0x8000) >> 16
                addu    addrTemp, addrTemp, base
                sdc1    src, (offset & 0xffff)(addrTemp)
              */
            m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16);
            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
            m_assembler.sdc1(src, addrTempRegister, address.offset);
        }
#endif
    }

    void addDouble(FPRegisterID src, FPRegisterID dest)
    {
        m_assembler.addd(dest, dest, src);
    }

    void addDouble(Address src, FPRegisterID dest)
    {
        loadDouble(src, fpTempRegister);
        m_assembler.addd(dest, dest, fpTempRegister);
    }

    void subDouble(FPRegisterID src, FPRegisterID dest)
    {
        m_assembler.subd(dest, dest, src);
    }

    void subDouble(Address src, FPRegisterID dest)
    {
        loadDouble(src, fpTempRegister);
        m_assembler.subd(dest, dest, fpTempRegister);
    }

    void mulDouble(FPRegisterID src, FPRegisterID dest)
    {
        m_assembler.muld(dest, dest, src);
    }

    void mulDouble(Address src, FPRegisterID dest)
    {
        loadDouble(src, fpTempRegister);
        m_assembler.muld(dest, dest, fpTempRegister);
    }

    void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
    {
        m_assembler.mtc1(src, fpTempRegister);
        m_assembler.cvtdw(dest, fpTempRegister);
    }

    void insertRelaxationWords()
    {
        /* We need four words for relaxation. */
        m_assembler.beq(MIPSRegisters::zero, MIPSRegisters::zero, 3); // Jump over nops;
        m_assembler.nop();
        m_assembler.nop();
        m_assembler.nop();
    }

    Jump branchTrue()
    {
        m_assembler.appendJump();
        m_assembler.bc1t();
        m_assembler.nop();
        insertRelaxationWords();
        return Jump(m_assembler.newJmpSrc());
    }

    Jump branchFalse()
    {
        m_assembler.appendJump();
        m_assembler.bc1f();
        m_assembler.nop();
        insertRelaxationWords();
        return Jump(m_assembler.newJmpSrc());
    }

    Jump branchEqual(RegisterID rs, RegisterID rt)
    {
        m_assembler.appendJump();
        m_assembler.beq(rs, rt, 0);
        m_assembler.nop();
        insertRelaxationWords();
        return Jump(m_assembler.newJmpSrc());
    }

    Jump branchNotEqual(RegisterID rs, RegisterID rt)
    {
        m_assembler.appendJump();
        m_assembler.bne(rs, rt, 0);
        m_assembler.nop();
        insertRelaxationWords();
        return Jump(m_assembler.newJmpSrc());
    }

    Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
    {
        if (cond == DoubleEqual) {
            m_assembler.ceqd(left, right);
            return branchTrue();
        }
        if (cond == DoubleNotEqual) {
            m_assembler.ceqd(left, right);
            return branchFalse(); // false
        }
        if (cond == DoubleGreaterThan) {
            m_assembler.cngtd(left, right);
            return branchFalse(); // false
        }
        if (cond == DoubleGreaterThanOrEqual) {
            m_assembler.cnged(right, left);
            return branchFalse(); // false
        }
        if (cond == DoubleLessThan) {
            m_assembler.cltd(left, right);
            return branchTrue();
        }
        if (cond == DoubleLessThanOrEqual) {
            m_assembler.cled(left, right);
            return branchTrue();
        }
        if (cond == DoubleEqualOrUnordered) {
            m_assembler.cueqd(left, right);
            return branchTrue();
        }
        if (cond == DoubleGreaterThanOrUnordered) {
            m_assembler.coled(left, right);
            return branchFalse(); // false
        }
        if (cond == DoubleGreaterThanOrEqualOrUnordered) {
            m_assembler.coltd(left, right);
            return branchFalse(); // false
        }
        if (cond == DoubleLessThanOrUnordered) {
            m_assembler.cultd(left, right);
            return branchTrue();
        }
        if (cond == DoubleLessThanOrEqualOrUnordered) {
            m_assembler.culed(left, right);
            return branchTrue();
        }
        ASSERT(0);

        return Jump();
    }

    // Truncates 'src' to an integer, and places the resulting 'dest'.
    // If the result is not representable as a 32 bit value, branch.
    // May also branch for some values that are representable in 32 bits
    // (specifically, in this case, INT_MAX 0x7fffffff).
    Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
    {
        m_assembler.truncwd(fpTempRegister, src);
        m_assembler.mfc1(dest, fpTempRegister);
        return branch32(Equal, dest, Imm32(0x7fffffff));
    }

private:
    // If m_fixedWidth is true, we will generate a fixed number of instructions.
    // Otherwise, we can emit any number of instructions.
    bool m_fixedWidth;

    friend class LinkBuffer;
    friend class RepatchBuffer;

    static void linkCall(void* code, Call call, FunctionPtr function)
    {
        MIPSAssembler::linkCall(code, call.m_jmp, function.value());
    }

    static void repatchCall(CodeLocationCall call, CodeLocationLabel destination)
    {
        MIPSAssembler::relinkCall(call.dataLocation(), destination.executableAddress());
    }

    static void repatchCall(CodeLocationCall call, FunctionPtr destination)
    {
        MIPSAssembler::relinkCall(call.dataLocation(), destination.executableAddress());
    }

};

}

#endif // ENABLE(ASSEMBLER) && CPU(MIPS)

#endif // MacroAssemblerMIPS_h



#include <e32std.h>
#endif

#if CPU(MIPS) && OS(LINUX)
#include <sys/cachectl.h>
#endif

#if OS(WINCE)
// From pkfuncs.h (private header file from the Platform Builder)
#define CACHE_SYNC_ALL 0x07F

    static void cacheFlush(void*, size_t)
    {
    }
#elif CPU(MIPS)
    static void cacheFlush(void* code, size_t size)
    {
#if COMPILER(GCC) && (GCC_VERSION >= 40300)
#if WTF_MIPS_ISA_REV(2) && (GCC_VERSION < 40403)
        int lineSize;
        asm ("rdhwr %0, $1" : "=r" (lineSize));
        //
        // Modify "start" and "end" to avoid GCC 4.3.0-4.4.2 bug in
        // mips_expand_synci_loop that may execute synci one more time.
        // "start" points to the fisrt byte of the cache line.
        // "end" points to the last byte of the line before the last cache line.
        // Because size is always a multiple of 4, this is safe to set
        // "end" to the last byte.
        //
        intptr_t start = reinterpret_cast<intptr_t>(code) & (-lineSize);
        intptr_t end = ((reinterpret_cast<intptr_t>(code) + size - 1) & (-lineSize)) - 1;
        __builtin___clear_cache(reinterpret_cast<char*>(start), reinterpret_cast<char*>(end));
#else
        intptr_t end = reinterpret_cast<intptr_t>(code) + size;
        __builtin___clear_cache(reinterpret_cast<char*>(code), reinterpret_cast<char*>(end));
#endif
#else
        _flush_cache(reinterpret_cast<char*>(code), size, BCACHE);
#endif
    }
#elif CPU(ARM_THUMB2) && OS(IPHONE_OS)
    static void cacheFlush(void* code, size_t size)
    {



        static const FPRegisterID fpRegT0 = ARMRegisters::d0;
        static const FPRegisterID fpRegT1 = ARMRegisters::d1;
        static const FPRegisterID fpRegT2 = ARMRegisters::d2;
#elif CPU(MIPS)
        static const RegisterID returnValueRegister = MIPSRegisters::v0;
        static const RegisterID cachedResultRegister = MIPSRegisters::v0;
        static const RegisterID firstArgumentRegister = MIPSRegisters::a0;

        // regT0 must be v0 for returning a 32-bit value.
        static const RegisterID regT0 = MIPSRegisters::v0;

        // regT1 must be v1 for returning a pair of 32-bit value.
        static const RegisterID regT1 = MIPSRegisters::v1;

        static const RegisterID regT2 = MIPSRegisters::t4;

        // regT3 must be saved in the callee, so use an S register.
        static const RegisterID regT3 = MIPSRegisters::s2;

        static const RegisterID callFrameRegister = MIPSRegisters::s0;
        static const RegisterID timeoutCheckRegister = MIPSRegisters::s1;

        static const FPRegisterID fpRegT0 = MIPSRegisters::f4;
        static const FPRegisterID fpRegT1 = MIPSRegisters::f6;
        static const FPRegisterID fpRegT2 = MIPSRegisters::f8;
#else
    #error "JIT not supported on this platform."
#endif

        // sequencePutById
        static const int sequencePutByIdInstructionSpace = 28;
        static const int sequencePutByIdConstantSpace = 3;
#elif CPU(MIPS)
#if WTF_MIPS_ISA(1)
        static const int patchOffsetPutByIdStructure = 16;
        static const int patchOffsetPutByIdExternalLoad = 48;
        static const int patchLengthPutByIdExternalLoad = 20;
        static const int patchOffsetPutByIdPropertyMapOffset = 68;
        static const int patchOffsetGetByIdStructure = 16;
        static const int patchOffsetGetByIdBranchToSlowCase = 48;
        static const int patchOffsetGetByIdExternalLoad = 48;
        static const int patchLengthGetByIdExternalLoad = 20;
        static const int patchOffsetGetByIdPropertyMapOffset = 68;
        static const int patchOffsetGetByIdPutResult = 88;
#if ENABLE(OPCODE_SAMPLING)
        #error "OPCODE_SAMPLING is not yet supported"
#else
        static const int patchOffsetGetByIdSlowCaseCall = 40;
#endif
        static const int patchOffsetOpCallCompareToJump = 32;
        static const int patchOffsetMethodCheckProtoObj = 32;
        static const int patchOffsetMethodCheckProtoStruct = 56;
        static const int patchOffsetMethodCheckPutFunction = 88;
#else // WTF_MIPS_ISA(1)
        static const int patchOffsetPutByIdStructure = 12;
        static const int patchOffsetPutByIdExternalLoad = 44;
        static const int patchLengthPutByIdExternalLoad = 16;
        static const int patchOffsetPutByIdPropertyMapOffset = 60;
        static const int patchOffsetGetByIdStructure = 12;
        static const int patchOffsetGetByIdBranchToSlowCase = 44;
        static const int patchOffsetGetByIdExternalLoad = 44;
        static const int patchLengthGetByIdExternalLoad = 16;
        static const int patchOffsetGetByIdPropertyMapOffset = 60;
        static const int patchOffsetGetByIdPutResult = 76;
#if ENABLE(OPCODE_SAMPLING)
        #error "OPCODE_SAMPLING is not yet supported"
#else
        static const int patchOffsetGetByIdSlowCaseCall = 40;
#endif
        static const int patchOffsetOpCallCompareToJump = 32;
        static const int patchOffsetMethodCheckProtoObj = 32;
        static const int patchOffsetMethodCheckProtoStruct = 52;
        static const int patchOffsetMethodCheckPutFunction = 84;
#endif
#endif
#endif // USE(JSVALUE32_64)




    loadPtr(address, linkRegister);
}

#elif CPU(MIPS)

ALWAYS_INLINE void JIT::preserveReturnAddressAfterCall(RegisterID reg)
{
    move(returnAddressRegister, reg);
}

ALWAYS_INLINE void JIT::restoreReturnAddressBeforeReturn(RegisterID reg)
{
    move(reg, returnAddressRegister);
}

ALWAYS_INLINE void JIT::restoreReturnAddressBeforeReturn(Address address)
{
    loadPtr(address, returnAddressRegister);
}

#else // CPU(X86) || CPU(X86_64)

ALWAYS_INLINE void JIT::preserveReturnAddressAfterCall(RegisterID reg)




    addPtr(Imm32(sizeof(ArgList)), stackPointerRegister);

#elif CPU(MIPS)
    emitGetFromCallFrameHeader32(RegisterFile::ArgumentCount, regT0);

    // Allocate stack space for our arglist
    COMPILE_ASSERT((sizeof(ArgList) & 0x7) == 0, ArgList_should_by_8byte_aligned);
    subPtr(Imm32(sizeof(ArgList) + 24), stackPointerRegister);

    // Set up arguments
    subPtr(Imm32(1), regT0); // Don't include 'this' in argcount

    // Push argcount to 24 + offset($sp)
    storePtr(regT0, Address(stackPointerRegister, 24 + OBJECT_OFFSETOF(ArgList, m_argCount)));

    // Calculate the start of the callframe header, and store in regT1
    move(callFrameRegister, regT1);
    sub32(Imm32(RegisterFile::CallFrameHeaderSize * (int32_t)sizeof(Register)), regT1);

    // Calculate start of arguments as callframe header - sizeof(Register) * argcount (regT1)
    mul32(Imm32(sizeof(Register)), regT0, regT0);
    subPtr(regT0, regT1);

    // push pointer to arguments to 24 + offset($sp)
    storePtr(regT1, Address(stackPointerRegister, 24 + OBJECT_OFFSETOF(ArgList, m_args)));

    // Setup arg3: regT1 currently points to the first argument, regT1-sizeof(Register) points to 'this'
    loadPtr(Address(regT1, -(int32_t)sizeof(Register)), MIPSRegisters::a3);

    // Setup arg2:
    emitGetFromCallFrameHeaderPtr(RegisterFile::Callee, MIPSRegisters::a2);

    // Setup arg1:
    move(callFrameRegister, MIPSRegisters::a1);

    // Setup arg4: ArgList is passed by reference.  At 16($sp), store ($sp + 24)
    addPtr(Imm32(24), stackPointerRegister, regT2);
    storePtr(regT2, Address(stackPointerRegister, 16));

    // Setup arg0 as 20($sp) to hold the returned structure.
    ASSERT(sizeof(JSValue) == 4);
    addPtr(Imm32(20), stackPointerRegister, MIPSRegisters::a0);

    // Call
    call(Address(MIPSRegisters::a2, OBJECT_OFFSETOF(JSFunction, m_data)));

    // Get returned value from 0($v0) which is the same as 20($sp)
    loadPtr(Address(returnValueRegister, 0), returnValueRegister);

    // Restore stack space
    addPtr(Imm32(sizeof(ArgList) + 24), stackPointerRegister);

#elif ENABLE(JIT_OPTIMIZE_NATIVE_CALL)
#error "JIT_OPTIMIZE_NATIVE_CALL not yet supported on this platform."
#else



    "mov pc, lr" "\n"
);

#elif CPU(MIPS)

#if USE(JIT_STUB_ARGUMENT_VA_LIST)
#error "JIT_STUB_ARGUMENT_VA_LIST not supported on MIPS."
#endif

asm volatile (
".text" "\n"
".align 2" "\n"
".set noreorder" "\n"
".set nomacro" "\n"
".set nomips16" "\n"
".globl " SYMBOL_STRING(ctiTrampoline) "\n"
".ent " SYMBOL_STRING(ctiTrampoline) "\n"
SYMBOL_STRING(ctiTrampoline) ":" "\n"
    "addiu $29,$29,-72" "\n"
    "sw    $31,44($29)" "\n"
    "sw    $18,40($29)" "\n"
    "sw    $17,36($29)" "\n"
    "sw    $16,32($29)" "\n"
#if WTF_MIPS_PIC
    "sw    $28,28($29)" "\n"
#endif
    "move  $16,$6       # set callFrameRegister" "\n"
    "li    $17,512      # set timeoutCheckRegister" "\n"
    "move  $25,$4       # move executableAddress to t9" "\n"
    "sw    $5,52($29)   # store registerFile to current stack" "\n"
    "sw    $6,56($29)   # store callFrame to curent stack" "\n"
    "sw    $7,60($29)   # store exception to current stack" "\n"
    "lw    $8,88($29)   # load enableProfilerReference from previous stack" "\n"
    "lw    $9,92($29)   # load globalData from previous stack" "\n"
    "sw    $8,64($29)   # store enableProfilerReference to current stack" "\n"
    "jalr  $25" "\n"
    "sw    $9,68($29)   # store globalData to current stack" "\n"
    "lw    $16,32($29)" "\n"
    "lw    $17,36($29)" "\n"
    "lw    $18,40($29)" "\n"
    "lw    $31,44($29)" "\n"
    "jr    $31" "\n"
    "addiu $29,$29,72" "\n"
".set reorder" "\n"
".set macro" "\n"
".end " SYMBOL_STRING(ctiTrampoline) "\n"
);

asm volatile (
".text" "\n"
".align 2" "\n"
".set noreorder" "\n"
".set nomacro" "\n"
".set nomips16" "\n"
".globl " SYMBOL_STRING(ctiVMThrowTrampoline) "\n"
".ent " SYMBOL_STRING(ctiVMThrowTrampoline) "\n"
SYMBOL_STRING(ctiVMThrowTrampoline) ":" "\n"
#if WTF_MIPS_PIC
    "lw    $28,28($29)" "\n"
".set macro" "\n"
    "la    $25," SYMBOL_STRING(cti_vm_throw) "\n"
".set nomacro" "\n"
    "bal " SYMBOL_STRING(cti_vm_throw) "\n"
    "move  $4,$29" "\n"
#else
    "jal " SYMBOL_STRING(cti_vm_throw) "\n"
    "move  $4,$29" "\n"
#endif
    "lw    $16,32($29)" "\n"
    "lw    $17,36($29)" "\n"
    "lw    $18,40($29)" "\n"
    "lw    $31,44($29)" "\n"
    "jr    $31" "\n"
    "addiu $29,$29,72" "\n"
".set reorder" "\n"
".set macro" "\n"
".end " SYMBOL_STRING(ctiVMThrowTrampoline) "\n"
);

asm volatile (
".text" "\n"
".align 2" "\n"
".set noreorder" "\n"
".set nomacro" "\n"
".set nomips16" "\n"
".globl " SYMBOL_STRING(ctiOpThrowNotCaught) "\n"
".ent " SYMBOL_STRING(ctiOpThrowNotCaught) "\n"
SYMBOL_STRING(ctiOpThrowNotCaught) ":" "\n"
    "lw    $16,32($29)" "\n"
    "lw    $17,36($29)" "\n"
    "lw    $18,40($29)" "\n"
    "lw    $31,44($29)" "\n"
    "jr    $31" "\n"
    "addiu $29,$29,72" "\n"
".set reorder" "\n"
".set macro" "\n"
".end " SYMBOL_STRING(ctiOpThrowNotCaught) "\n"
);

#elif COMPILER(RVCT) && CPU(ARM_TRADITIONAL)

__asm EncodedJSValue ctiTrampoline(void*, RegisterFile*, CallFrame*, JSValue*, Profiler**, JSGlobalData*)


    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, thunkReturnAddress) == 0x1C);
#endif

#if CPU(MIPS)
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedGP) == 28);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedS0) == 32);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedS1) == 36);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedS2) == 40);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedReturnAddress) == 44);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, thunkReturnAddress) == 48);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, registerFile) == 52);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, callFrame) == 56);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, exception) == 60);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, enabledProfilerReference) == 64);
    ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, globalData) == 68);

#endif
}

#if ENABLE(JIT_OPTIMIZE_PROPERTY_ACCESS)

        ); \
    rtype JITStubThunked_##op(STUB_ARGS_DECLARATION) \

#elif CPU(MIPS)
#if WTF_MIPS_PIC
#define DEFINE_STUB_FUNCTION(rtype, op) \
    extern "C" { \
        rtype JITStubThunked_##op(STUB_ARGS_DECLARATION); \
    }; \
    asm volatile ( \
        ".text" "\n" \
        ".align 2" "\n" \
        ".set noreorder" "\n" \
        ".set nomacro" "\n" \
        ".set nomips16" "\n" \
        ".globl " SYMBOL_STRING(cti_##op) "\n" \
        ".ent " SYMBOL_STRING(cti_##op) "\n" \
        SYMBOL_STRING(cti_##op) ":" "\n" \
        "lw    $28,28($29)" "\n" \
        "sw    $31,48($29)" "\n" \
        ".set macro" "\n" \
        "la    $25," SYMBOL_STRING(JITStubThunked_##op) "\n" \
        ".set nomacro" "\n" \
        "bal " SYMBOL_STRING(JITStubThunked_##op) "\n" \
        "nop" "\n" \
        "lw    $31,48($29)" "\n" \
        "jr    $31" "\n" \
        "nop" "\n" \
        ".set reorder" "\n" \
        ".set macro" "\n" \
        ".end " SYMBOL_STRING(cti_##op) "\n" \
        ); \
    rtype JITStubThunked_##op(STUB_ARGS_DECLARATION)

#else // WTF_MIPS_PIC
#define DEFINE_STUB_FUNCTION(rtype, op) \
    extern "C" { \
        rtype JITStubThunked_##op(STUB_ARGS_DECLARATION); \
    }; \
    asm volatile ( \
        ".text" "\n" \
        ".align 2" "\n" \
        ".set noreorder" "\n" \
        ".set nomacro" "\n" \
        ".set nomips16" "\n" \
        ".globl " SYMBOL_STRING(cti_##op) "\n" \
        ".ent " SYMBOL_STRING(cti_##op) "\n" \
        SYMBOL_STRING(cti_##op) ":" "\n" \
        "sw    $31,48($29)" "\n" \
        "jal " SYMBOL_STRING(JITStubThunked_##op) "\n" \
        "nop" "\n" \
        "lw    $31,48($29)" "\n" \
        "jr    $31" "\n" \
        "nop" "\n" \
        ".set reorder" "\n" \
        ".set macro" "\n" \
        ".end " SYMBOL_STRING(cti_##op) "\n" \
        ); \
    rtype JITStubThunked_##op(STUB_ARGS_DECLARATION)

#endif

#elif CPU(ARM_TRADITIONAL) && COMPILER(GCC)

#if USE(JSVALUE32_64)



        // When JIT code makes a call, it pushes its return address just below the rest of the stack.
        ReturnAddressPtr* returnAddressSlot() { return &thunkReturnAddress; }
    };
#elif CPU(MIPS)
    struct JITStackFrame {
        void* reserved; // Unused
        JITStubArg args[6];

        void* preservedGP; // store GP when using PIC code
        void* preservedS0;
        void* preservedS1;
        void* preservedS2;
        void* preservedReturnAddress;

        ReturnAddressPtr thunkReturnAddress;

        // These arguments passed in a1..a3 (a0 contained the entry code pointed, which is not preserved)
        RegisterFile* registerFile;
        CallFrame* callFrame;
        JSValue* exception;

        // These arguments passed on the stack.
        Profiler** enabledProfilerReference;
        JSGlobalData* globalData;

        ReturnAddressPtr* returnAddressSlot() { return &thunkReturnAddress; }
    };
#else
#error "JITStackFrame not defined for this platform."
#endif



#define WTF_CPU_IA64 1
#endif

/* CPU(MIPS) - MIPS 32-bit */
/* Note: Only O32 ABI is tested, so we enable it for O32 ABI for now.  */
#if   (defined(mips) || defined(__mips__)) && defined(_ABIO32)
#define WTF_CPU_MIPS 1
#if defined(__MIPSEB__)
#define WTF_CPU_BIG_ENDIAN 1
#endif
#define WTF_MIPS_PIC (defined __PIC__)
#define WTF_MIPS_ARCH __mips
#define WTF_MIPS_ISA(v) (defined WTF_MIPS_ARCH && WTF_MIPS_ARCH == v)
#define WTF_MIPS_ISA_AT_LEAST(v) (defined WTF_MIPS_ARCH && WTF_MIPS_ARCH >= v)
#define WTF_MIPS_ARCH_REV __mips_isa_rev
#define WTF_MIPS_ISA_REV(v) (defined WTF_MIPS_ARCH_REV && WTF_MIPS_ARCH_REV == v)
#define WTF_MIPS_DOUBLE_FLOAT (defined __mips_hard_float && !defined __mips_single_float)
#endif /* MIPS */

/* CPU(PPC) - PowerPC 32-bit */
#if   defined(__ppc__)     \
    || defined(__PPC__)     \

#if !defined(WTF_USE_JSVALUE64) && !defined(WTF_USE_JSVALUE32) && !defined(WTF_USE_JSVALUE32_64)
#if (CPU(X86_64) && (OS(UNIX) || OS(WINDOWS))) || CPU(IA64) || CPU(ALPHA)
#define WTF_USE_JSVALUE64 1
#elif CPU(ARM) || CPU(PPC64) || CPU(MIPS)
#define WTF_USE_JSVALUE32 1
#elif OS(WINDOWS) && COMPILER(MINGW)
/* Using JSVALUE32_64 causes padding/alignement issues for JITStubArg

    #define ENABLE_JIT 1
#elif CPU(ARM_TRADITIONAL) && OS(LINUX)
    #define ENABLE_JIT 1
#elif CPU(MIPS) && OS(LINUX)
    #define ENABLE_JIT 1
    #define WTF_USE_JIT_STUB_ARGUMENT_VA_LIST 0
#endif
#endif /* PLATFORM(QT) */


    || (CPU(X86) && OS(WINDOWS) && COMPILER(MSVC)) \
    || (CPU(X86) && OS(LINUX) && GCC_VERSION >= 40100) \
    || (CPU(X86_64) && OS(LINUX) && GCC_VERSION >= 40100) \
    || (CPU(ARM_TRADITIONAL) && OS(LINUX)) \
    || (CPU(MIPS) && OS(LINUX))
#define ENABLE_YARR 1
#define ENABLE_YARR_JIT 1
#endif

Lines 54-59 class RegexGenerator : private MacroAsse JavaScriptCore/yarr/RegexJIT.cpp_sec1
- JavaScriptCore/yarr/RegexJIT.cpp +14 lines
54	static const RegisterID regT1 = ARMRegisters::r6;	54	static const RegisterID regT1 = ARMRegisters::r6;
55		55
56	static const RegisterID returnRegister = ARMRegisters::r0;	56	static const RegisterID returnRegister = ARMRegisters::r0;
		57	#elif CPU(MIPS)
		58	static const RegisterID input = MIPSRegisters::a0;
		59	static const RegisterID index = MIPSRegisters::a1;
		60	static const RegisterID length = MIPSRegisters::a2;
		61	static const RegisterID output = MIPSRegisters::a3;
		62
		63	static const RegisterID regT0 = MIPSRegisters::t4;
		64	static const RegisterID regT1 = MIPSRegisters::t5;
		65
		66	static const RegisterID returnRegister = MIPSRegisters::v0;
57	#elif CPU(X86)	67	#elif CPU(X86)
58	static const RegisterID input = X86Registers::eax;	68	static const RegisterID input = X86Registers::eax;
59	static const RegisterID index = X86Registers::edx;	69	static const RegisterID index = X86Registers::edx;
Lines 1313-1318 class RegexGenerator : private MacroAsse JavaScriptCore/yarr/RegexJIT.cpp_sec2
1313	push(ARMRegisters::r5);	1323	push(ARMRegisters::r5);
1314	push(ARMRegisters::r6);	1324	push(ARMRegisters::r6);
1315	move(ARMRegisters::r3, output);	1325	move(ARMRegisters::r3, output);
		1326	#elif CPU(MIPS)
		1327	// Do nothing.
1316	#endif	1328	#endif
1317	}	1329	}
1318		1330
Lines 1330-1335 class RegexGenerator : private MacroAsse JavaScriptCore/yarr/RegexJIT.cpp_sec3
1330	pop(ARMRegisters::r6);	1342	pop(ARMRegisters::r6);
1331	pop(ARMRegisters::r5);	1343	pop(ARMRegisters::r5);
1332	pop(ARMRegisters::r4);	1344	pop(ARMRegisters::r4);
		1345	#elif CPU(MIPS)
		1346	// Do nothing
1333	#endif	1347	#endif
1334	ret();	1348	ret();
1335	}	1349	}

Return to Bug 30144

Lines 173-179 public: JavaScriptCore/assembler/AbstractMacroAssembler.h_sec1
- JavaScriptCore/assembler/AbstractMacroAssembler.h -3 / +4 lines
173	struct Imm32 {	173	struct Imm32 {
174	explicit Imm32(int32_t value)	174	explicit Imm32(int32_t value)
175	: m_value(value)	175	: m_value(value)
176	#if CPU(ARM)	176	#if CPU(ARM) \|\| CPU(MIPS)
177	, m_isPointer(false)	177	, m_isPointer(false)
178	#endif	178	#endif
179	{	179	{
Lines 182-188 public: JavaScriptCore/assembler/AbstractMacroAssembler.h_sec2
182	#if !CPU(X86_64)	182	#if !CPU(X86_64)
183	explicit Imm32(ImmPtr ptr)	183	explicit Imm32(ImmPtr ptr)
184	: m_value(ptr.asIntptr())	184	: m_value(ptr.asIntptr())
185	#if CPU(ARM)	185	#if CPU(ARM) \|\| CPU(MIPS)
186	, m_isPointer(true)	186	, m_isPointer(true)
187	#endif	187	#endif
188	{	188	{
Lines 190-202 public: JavaScriptCore/assembler/AbstractMacroAssembler.h_sec3
190	#endif	190	#endif
191		191
192	int32_t m_value;	192	int32_t m_value;
193	#if CPU(ARM)	193	#if CPU(ARM) \|\| CPU(MIPS)
194	// We rely on being able to regenerate code to recover exception handling	194	// We rely on being able to regenerate code to recover exception handling
195	// information. Since ARMv7 supports 16-bit immediates there is a danger	195	// information. Since ARMv7 supports 16-bit immediates there is a danger
196	// that if pointer values change the layout of the generated code will change.	196	// that if pointer values change the layout of the generated code will change.
197	// To avoid this problem, always generate pointers (and thus Imm32s constructed	197	// To avoid this problem, always generate pointers (and thus Imm32s constructed
198	// from ImmPtrs) with a code sequence that is able to represent any pointer	198	// from ImmPtrs) with a code sequence that is able to represent any pointer
199	// value - don't use a more compact form in these cases.	199	// value - don't use a more compact form in these cases.
		200	// Same for MIPS.
200	bool m_isPointer;	201	bool m_isPointer;
201	#endif	202	#endif
202	};	203	};

Lines 268-273 namespace JSC { JavaScriptCore/jit/JIT.h_sec1
- JavaScriptCore/jit/JIT.h +64 lines
268	static const FPRegisterID fpRegT0 = ARMRegisters::d0;	268	static const FPRegisterID fpRegT0 = ARMRegisters::d0;
269	static const FPRegisterID fpRegT1 = ARMRegisters::d1;	269	static const FPRegisterID fpRegT1 = ARMRegisters::d1;
270	static const FPRegisterID fpRegT2 = ARMRegisters::d2;	270	static const FPRegisterID fpRegT2 = ARMRegisters::d2;
		271	#elif CPU(MIPS)
		272	static const RegisterID returnValueRegister = MIPSRegisters::v0;
		273	static const RegisterID cachedResultRegister = MIPSRegisters::v0;
		274	static const RegisterID firstArgumentRegister = MIPSRegisters::a0;
		275
		276	// regT0 must be v0 for returning a 32-bit value.
		277	static const RegisterID regT0 = MIPSRegisters::v0;
		278
		279	// regT1 must be v1 for returning a pair of 32-bit value.
		280	static const RegisterID regT1 = MIPSRegisters::v1;
		281
		282	static const RegisterID regT2 = MIPSRegisters::t4;
		283
		284	// regT3 must be saved in the callee, so use an S register.
		285	static const RegisterID regT3 = MIPSRegisters::s2;
		286
		287	static const RegisterID callFrameRegister = MIPSRegisters::s0;
		288	static const RegisterID timeoutCheckRegister = MIPSRegisters::s1;
		289
		290	static const FPRegisterID fpRegT0 = MIPSRegisters::f4;
		291	static const FPRegisterID fpRegT1 = MIPSRegisters::f6;
		292	static const FPRegisterID fpRegT2 = MIPSRegisters::f8;
271	#else	293	#else
272	#error "JIT not supported on this platform."	294	#error "JIT not supported on this platform."
273	#endif	295	#endif
Lines 686-691 namespace JSC { JavaScriptCore/jit/JIT.h_sec2
686	// sequencePutById	708	// sequencePutById
687	static const int sequencePutByIdInstructionSpace = 28;	709	static const int sequencePutByIdInstructionSpace = 28;
688	static const int sequencePutByIdConstantSpace = 3;	710	static const int sequencePutByIdConstantSpace = 3;
		711	#elif CPU(MIPS)
		712	#if WTF_MIPS_ISA(1)
		713	static const int patchOffsetPutByIdStructure = 16;
		714	static const int patchOffsetPutByIdExternalLoad = 48;
		715	static const int patchLengthPutByIdExternalLoad = 20;
		716	static const int patchOffsetPutByIdPropertyMapOffset = 68;
		717	static const int patchOffsetGetByIdStructure = 16;
		718	static const int patchOffsetGetByIdBranchToSlowCase = 48;
		719	static const int patchOffsetGetByIdExternalLoad = 48;
		720	static const int patchLengthGetByIdExternalLoad = 20;
		721	static const int patchOffsetGetByIdPropertyMapOffset = 68;
		722	static const int patchOffsetGetByIdPutResult = 88;
		723	#if ENABLE(OPCODE_SAMPLING)
		724	#error "OPCODE_SAMPLING is not yet supported"
		725	#else
		726	static const int patchOffsetGetByIdSlowCaseCall = 40;
		727	#endif
		728	static const int patchOffsetOpCallCompareToJump = 32;
		729	static const int patchOffsetMethodCheckProtoObj = 32;
		730	static const int patchOffsetMethodCheckProtoStruct = 56;
		731	static const int patchOffsetMethodCheckPutFunction = 88;
		732	#else // WTF_MIPS_ISA(1)
		733	static const int patchOffsetPutByIdStructure = 12;
		734	static const int patchOffsetPutByIdExternalLoad = 44;
		735	static const int patchLengthPutByIdExternalLoad = 16;
		736	static const int patchOffsetPutByIdPropertyMapOffset = 60;
		737	static const int patchOffsetGetByIdStructure = 12;
		738	static const int patchOffsetGetByIdBranchToSlowCase = 44;
		739	static const int patchOffsetGetByIdExternalLoad = 44;
		740	static const int patchLengthGetByIdExternalLoad = 16;
		741	static const int patchOffsetGetByIdPropertyMapOffset = 60;
		742	static const int patchOffsetGetByIdPutResult = 76;
		743	#if ENABLE(OPCODE_SAMPLING)
		744	#error "OPCODE_SAMPLING is not yet supported"
		745	#else
		746	static const int patchOffsetGetByIdSlowCaseCall = 40;
		747	#endif
		748	static const int patchOffsetOpCallCompareToJump = 32;
		749	static const int patchOffsetMethodCheckProtoObj = 32;
		750	static const int patchOffsetMethodCheckProtoStruct = 52;
		751	static const int patchOffsetMethodCheckPutFunction = 84;
		752	#endif
689	#endif	753	#endif
690	#endif // USE(JSVALUE32_64)	754	#endif // USE(JSVALUE32_64)
691		755

Lines 161-166 ALWAYS_INLINE void JIT::restoreReturnAdd JavaScriptCore/jit/JITInlineMethods.h_sec1
- JavaScriptCore/jit/JITInlineMethods.h +17 lines
161	loadPtr(address, linkRegister);	161	loadPtr(address, linkRegister);
162	}	162	}
163		163
		164	#elif CPU(MIPS)
		165
		166	ALWAYS_INLINE void JIT::preserveReturnAddressAfterCall(RegisterID reg)
		167	{
		168	move(returnAddressRegister, reg);
		169	}
		170
		171	ALWAYS_INLINE void JIT::restoreReturnAddressBeforeReturn(RegisterID reg)
		172	{
		173	move(reg, returnAddressRegister);
		174	}
		175
		176	ALWAYS_INLINE void JIT::restoreReturnAddressBeforeReturn(Address address)
		177	{
		178	loadPtr(address, returnAddressRegister);
		179	}
		180
164	#else // CPU(X86) \|\| CPU(X86_64)	181	#else // CPU(X86) \|\| CPU(X86_64)
165		182
166	ALWAYS_INLINE void JIT::preserveReturnAddressAfterCall(RegisterID reg)	183	ALWAYS_INLINE void JIT::preserveReturnAddressAfterCall(RegisterID reg)

Lines 1780-1785 void JIT::privateCompileCTIMachineTrampo JavaScriptCore/jit/JITOpcodes.cpp_sec1
- JavaScriptCore/jit/JITOpcodes.cpp +50 lines
1780		1780
1781	addPtr(Imm32(sizeof(ArgList)), stackPointerRegister);	1781	addPtr(Imm32(sizeof(ArgList)), stackPointerRegister);
1782		1782
		1783	#elif CPU(MIPS)
		1784	emitGetFromCallFrameHeader32(RegisterFile::ArgumentCount, regT0);
		1785
		1786	// Allocate stack space for our arglist
		1787	COMPILE_ASSERT((sizeof(ArgList) & 0x7) == 0, ArgList_should_by_8byte_aligned);
		1788	subPtr(Imm32(sizeof(ArgList) + 24), stackPointerRegister);
		1789
		1790	// Set up arguments
		1791	subPtr(Imm32(1), regT0); // Don't include 'this' in argcount
		1792
		1793	// Push argcount to 24 + offset($sp)
		1794	storePtr(regT0, Address(stackPointerRegister, 24 + OBJECT_OFFSETOF(ArgList, m_argCount)));
		1795
		1796	// Calculate the start of the callframe header, and store in regT1
		1797	move(callFrameRegister, regT1);
		1798	sub32(Imm32(RegisterFile::CallFrameHeaderSize * (int32_t)sizeof(Register)), regT1);
		1799
		1800	// Calculate start of arguments as callframe header - sizeof(Register) * argcount (regT1)
		1801	mul32(Imm32(sizeof(Register)), regT0, regT0);
		1802	subPtr(regT0, regT1);
		1803
		1804	// push pointer to arguments to 24 + offset($sp)
		1805	storePtr(regT1, Address(stackPointerRegister, 24 + OBJECT_OFFSETOF(ArgList, m_args)));
		1806
		1807	// Setup arg3: regT1 currently points to the first argument, regT1-sizeof(Register) points to 'this'
		1808	loadPtr(Address(regT1, -(int32_t)sizeof(Register)), MIPSRegisters::a3);
		1809
		1810	// Setup arg2:
		1811	emitGetFromCallFrameHeaderPtr(RegisterFile::Callee, MIPSRegisters::a2);
		1812
		1813	// Setup arg1:
		1814	move(callFrameRegister, MIPSRegisters::a1);
		1815
		1816	// Setup arg4: ArgList is passed by reference. At 16($sp), store ($sp + 24)
		1817	addPtr(Imm32(24), stackPointerRegister, regT2);
		1818	storePtr(regT2, Address(stackPointerRegister, 16));
		1819
		1820	// Setup arg0 as 20($sp) to hold the returned structure.
		1821	ASSERT(sizeof(JSValue) == 4);
		1822	addPtr(Imm32(20), stackPointerRegister, MIPSRegisters::a0);
		1823
		1824	// Call
		1825	call(Address(MIPSRegisters::a2, OBJECT_OFFSETOF(JSFunction, m_data)));
		1826
		1827	// Get returned value from 0($v0) which is the same as 20($sp)
		1828	loadPtr(Address(returnValueRegister, 0), returnValueRegister);
		1829
		1830	// Restore stack space
		1831	addPtr(Imm32(sizeof(ArgList) + 24), stackPointerRegister);
		1832
1783	#elif ENABLE(JIT_OPTIMIZE_NATIVE_CALL)	1833	#elif ENABLE(JIT_OPTIMIZE_NATIVE_CALL)
1784	#error "JIT_OPTIMIZE_NATIVE_CALL not yet supported on this platform."	1834	#error "JIT_OPTIMIZE_NATIVE_CALL not yet supported on this platform."
1785	#else	1835	#else

Lines 642-647 SYMBOL_STRING(ctiOpThrowNotCaught) ":" " JavaScriptCore/jit/JITStubs.cpp_sec1
- JavaScriptCore/jit/JITStubs.cpp +170 lines
642	"mov pc, lr" "\n"	642	"mov pc, lr" "\n"
643	);	643	);
644		644
		645	#elif CPU(MIPS)
		646
		647	#if USE(JIT_STUB_ARGUMENT_VA_LIST)
		648	#error "JIT_STUB_ARGUMENT_VA_LIST not supported on MIPS."
		649	#endif
		650
		651	asm volatile (
		652	".text" "\n"
		653	".align 2" "\n"
		654	".set noreorder" "\n"
		655	".set nomacro" "\n"
		656	".set nomips16" "\n"
		657	".globl " SYMBOL_STRING(ctiTrampoline) "\n"
		658	".ent " SYMBOL_STRING(ctiTrampoline) "\n"
		659	SYMBOL_STRING(ctiTrampoline) ":" "\n"
		660	"addiu $29,$29,-72" "\n"
		661	"sw $31,44($29)" "\n"
		662	"sw $18,40($29)" "\n"
		663	"sw $17,36($29)" "\n"
		664	"sw $16,32($29)" "\n"
		665	#if WTF_MIPS_PIC
		666	"sw $28,28($29)" "\n"
		667	#endif
		668	"move $16,$6 # set callFrameRegister" "\n"
		669	"li $17,512 # set timeoutCheckRegister" "\n"
		670	"move $25,$4 # move executableAddress to t9" "\n"
		671	"sw $5,52($29) # store registerFile to current stack" "\n"
		672	"sw $6,56($29) # store callFrame to curent stack" "\n"
		673	"sw $7,60($29) # store exception to current stack" "\n"
		674	"lw $8,88($29) # load enableProfilerReference from previous stack" "\n"
		675	"lw $9,92($29) # load globalData from previous stack" "\n"
		676	"sw $8,64($29) # store enableProfilerReference to current stack" "\n"
		677	"jalr $25" "\n"
		678	"sw $9,68($29) # store globalData to current stack" "\n"
		679	"lw $16,32($29)" "\n"
		680	"lw $17,36($29)" "\n"
		681	"lw $18,40($29)" "\n"
		682	"lw $31,44($29)" "\n"
		683	"jr $31" "\n"
		684	"addiu $29,$29,72" "\n"
		685	".set reorder" "\n"
		686	".set macro" "\n"
		687	".end " SYMBOL_STRING(ctiTrampoline) "\n"
		688	);
		689
		690	asm volatile (
		691	".text" "\n"
		692	".align 2" "\n"
		693	".set noreorder" "\n"
		694	".set nomacro" "\n"
		695	".set nomips16" "\n"
		696	".globl " SYMBOL_STRING(ctiVMThrowTrampoline) "\n"
		697	".ent " SYMBOL_STRING(ctiVMThrowTrampoline) "\n"
		698	SYMBOL_STRING(ctiVMThrowTrampoline) ":" "\n"
		699	#if WTF_MIPS_PIC
		700	"lw $28,28($29)" "\n"
		701	".set macro" "\n"
		702	"la $25," SYMBOL_STRING(cti_vm_throw) "\n"
		703	".set nomacro" "\n"
		704	"bal " SYMBOL_STRING(cti_vm_throw) "\n"
		705	"move $4,$29" "\n"
		706	#else
		707	"jal " SYMBOL_STRING(cti_vm_throw) "\n"
		708	"move $4,$29" "\n"
709	#endif
710	"lw $16,32($29)" "\n"
711	"lw $17,36($29)" "\n"
712	"lw $18,40($29)" "\n"
713	"lw $31,44($29)" "\n"
714	"jr $31" "\n"
715	"addiu $29,$29,72" "\n"
716	".set reorder" "\n"
717	".set macro" "\n"
718	".end " SYMBOL_STRING(ctiVMThrowTrampoline) "\n"
719	);
720
721	asm volatile (
722	".text" "\n"
723	".align 2" "\n"
724	".set noreorder" "\n"
725	".set nomacro" "\n"
726	".set nomips16" "\n"
727	".globl " SYMBOL_STRING(ctiOpThrowNotCaught) "\n"
728	".ent " SYMBOL_STRING(ctiOpThrowNotCaught) "\n"
729	SYMBOL_STRING(ctiOpThrowNotCaught) ":" "\n"
730	"lw $16,32($29)" "\n"
731	"lw $17,36($29)" "\n"
732	"lw $18,40($29)" "\n"
733	"lw $31,44($29)" "\n"
734	"jr $31" "\n"
735	"addiu $29,$29,72" "\n"
736	".set reorder" "\n"
737	".set macro" "\n"
738	".end " SYMBOL_STRING(ctiOpThrowNotCaught) "\n"
739	);
740
645	#elif COMPILER(RVCT) && CPU(ARM_TRADITIONAL)	741	#elif COMPILER(RVCT) && CPU(ARM_TRADITIONAL)
646		742
647	__asm EncodedJSValue ctiTrampoline(void, RegisterFile, CallFrame, JSValue, Profiler*, JSGlobalData)	743	__asm EncodedJSValue ctiTrampoline(void, RegisterFile, CallFrame, JSValue, Profiler*, JSGlobalData)
Lines 777-782 JITThunks::JITThunks(JSGlobalData* globa JavaScriptCore/jit/JITStubs.cpp_sec2
777		873
778	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, thunkReturnAddress) == 0x1C);	874	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, thunkReturnAddress) == 0x1C);
779	#endif	875	#endif
		876
		877	#if CPU(MIPS)
		878	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedGP) == 28);
		879	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedS0) == 32);
		880	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedS1) == 36);
		881	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedS2) == 40);
		882	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, preservedReturnAddress) == 44);
		883	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, thunkReturnAddress) == 48);
		884	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, registerFile) == 52);
		885	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, callFrame) == 56);
		886	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, exception) == 60);
		887	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, enabledProfilerReference) == 64);
		888	ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, globalData) == 68);
		889
		890	#endif
780	}	891	}
781		892
782	#if ENABLE(JIT_OPTIMIZE_PROPERTY_ACCESS)	893	#if ENABLE(JIT_OPTIMIZE_PROPERTY_ACCESS)
Lines 1034-1039 static NEVER_INLINE void throwStackOverf JavaScriptCore/jit/JITStubs.cpp_sec3
1034	); \	1145	); \
1035	rtype JITStubThunked_##op(STUB_ARGS_DECLARATION) \	1146	rtype JITStubThunked_##op(STUB_ARGS_DECLARATION) \
1036		1147
		1148	#elif CPU(MIPS)
		1149	#if WTF_MIPS_PIC
		1150	#define DEFINE_STUB_FUNCTION(rtype, op) \
		1151	extern "C" { \
		1152	rtype JITStubThunked_##op(STUB_ARGS_DECLARATION); \
		1153	}; \
		1154	asm volatile ( \
		1155	".text" "\n" \
		1156	".align 2" "\n" \
		1157	".set noreorder" "\n" \
		1158	".set nomacro" "\n" \
		1159	".set nomips16" "\n" \
		1160	".globl " SYMBOL_STRING(cti_##op) "\n" \
		1161	".ent " SYMBOL_STRING(cti_##op) "\n" \
		1162	SYMBOL_STRING(cti_##op) ":" "\n" \
		1163	"lw $28,28($29)" "\n" \
		1164	"sw $31,48($29)" "\n" \
		1165	".set macro" "\n" \
		1166	"la $25," SYMBOL_STRING(JITStubThunked_##op) "\n" \
		1167	".set nomacro" "\n" \
		1168	"bal " SYMBOL_STRING(JITStubThunked_##op) "\n" \
		1169	"nop" "\n" \
		1170	"lw $31,48($29)" "\n" \
		1171	"jr $31" "\n" \
		1172	"nop" "\n" \
		1173	".set reorder" "\n" \
		1174	".set macro" "\n" \
		1175	".end " SYMBOL_STRING(cti_##op) "\n" \
		1176	); \
		1177	rtype JITStubThunked_##op(STUB_ARGS_DECLARATION)
		1178
		1179	#else // WTF_MIPS_PIC
		1180	#define DEFINE_STUB_FUNCTION(rtype, op) \
		1181	extern "C" { \
		1182	rtype JITStubThunked_##op(STUB_ARGS_DECLARATION); \
		1183	}; \
		1184	asm volatile ( \
		1185	".text" "\n" \
		1186	".align 2" "\n" \
		1187	".set noreorder" "\n" \
		1188	".set nomacro" "\n" \
		1189	".set nomips16" "\n" \
		1190	".globl " SYMBOL_STRING(cti_##op) "\n" \
		1191	".ent " SYMBOL_STRING(cti_##op) "\n" \
		1192	SYMBOL_STRING(cti_##op) ":" "\n" \
		1193	"sw $31,48($29)" "\n" \
		1194	"jal " SYMBOL_STRING(JITStubThunked_##op) "\n" \
		1195	"nop" "\n" \
		1196	"lw $31,48($29)" "\n" \
		1197	"jr $31" "\n" \
		1198	"nop" "\n" \
		1199	".set reorder" "\n" \
		1200	".set macro" "\n" \
		1201	".end " SYMBOL_STRING(cti_##op) "\n" \
		1202	); \
		1203	rtype JITStubThunked_##op(STUB_ARGS_DECLARATION)
		1204
		1205	#endif
		1206
1037	#elif CPU(ARM_TRADITIONAL) && COMPILER(GCC)	1207	#elif CPU(ARM_TRADITIONAL) && COMPILER(GCC)
1038		1208
1039	#if USE(JSVALUE32_64)	1209	#if USE(JSVALUE32_64)

Lines 1-3 JavaScriptCore/ChangeLog_sec1
- JavaScriptCore/ChangeLog +182 lines
		1	2010-02-25 Chao-ying Fu <fu@mips.com>
		2
		3	Reviewed by NOBODY (OOPS!).
		4
		5	MIPS JIT Supports
		6	https://bugs.webkit.org/show_bug.cgi?id=30144
		7
		8	The following changes are for MIPS JIT.
		9
		10	* assembler/AbstractMacroAssembler.h:
		11	(JSC::AbstractMacroAssembler::Imm32::Imm32):
		12	* assembler/MIPSAssembler.h: Added.
		13	(JSC::MIPSRegisters::):
		14	(JSC::MIPSAssembler::MIPSAssembler):
		15	(JSC::MIPSAssembler::):
		16	(JSC::MIPSAssembler::JmpSrc::JmpSrc):
		17	(JSC::MIPSAssembler::JmpDst::JmpDst):
		18	(JSC::MIPSAssembler::JmpDst::isUsed):
		19	(JSC::MIPSAssembler::JmpDst::used):
		20	(JSC::MIPSAssembler::emitInst):
		21	(JSC::MIPSAssembler::nop):
		22	(JSC::MIPSAssembler::loadDelayNop):
		23	(JSC::MIPSAssembler::copDelayNop):
		24	(JSC::MIPSAssembler::move):
		25	(JSC::MIPSAssembler::li):
		26	(JSC::MIPSAssembler::lui):
		27	(JSC::MIPSAssembler::addiu):
		28	(JSC::MIPSAssembler::addu):
		29	(JSC::MIPSAssembler::subu):
		30	(JSC::MIPSAssembler::mult):
		31	(JSC::MIPSAssembler::mfhi):
		32	(JSC::MIPSAssembler::mflo):
		33	(JSC::MIPSAssembler::mul):
		34	(JSC::MIPSAssembler::andInsn):
		35	(JSC::MIPSAssembler::andi):
		36	(JSC::MIPSAssembler::nor):
		37	(JSC::MIPSAssembler::orInsn):
		38	(JSC::MIPSAssembler::ori):
		39	(JSC::MIPSAssembler::xorInsn):
		40	(JSC::MIPSAssembler::xori):
		41	(JSC::MIPSAssembler::slt):
		42	(JSC::MIPSAssembler::sltu):
		43	(JSC::MIPSAssembler::sltiu):
		44	(JSC::MIPSAssembler::sll):
		45	(JSC::MIPSAssembler::sllv):
		46	(JSC::MIPSAssembler::sra):
		47	(JSC::MIPSAssembler::srav):
		48	(JSC::MIPSAssembler::lw):
		49	(JSC::MIPSAssembler::lwl):
		50	(JSC::MIPSAssembler::lwr):
		51	(JSC::MIPSAssembler::lhu):
		52	(JSC::MIPSAssembler::sw):
		53	(JSC::MIPSAssembler::jr):
		54	(JSC::MIPSAssembler::jalr):
		55	(JSC::MIPSAssembler::jal):
		56	(JSC::MIPSAssembler::bkpt):
		57	(JSC::MIPSAssembler::bgez):
		58	(JSC::MIPSAssembler::bltz):
		59	(JSC::MIPSAssembler::beq):
		60	(JSC::MIPSAssembler::bne):
		61	(JSC::MIPSAssembler::bc1t):
		62	(JSC::MIPSAssembler::bc1f):
		63	(JSC::MIPSAssembler::newJmpSrc):
		64	(JSC::MIPSAssembler::appendJump):
65	(JSC::MIPSAssembler::addd):
66	(JSC::MIPSAssembler::subd):
67	(JSC::MIPSAssembler::muld):
68	(JSC::MIPSAssembler::lwc1):
69	(JSC::MIPSAssembler::ldc1):
70	(JSC::MIPSAssembler::swc1):
71	(JSC::MIPSAssembler::sdc1):
72	(JSC::MIPSAssembler::mtc1):
73	(JSC::MIPSAssembler::mfc1):
74	(JSC::MIPSAssembler::truncwd):
75	(JSC::MIPSAssembler::cvtdw):
76	(JSC::MIPSAssembler::ceqd):
77	(JSC::MIPSAssembler::cngtd):
78	(JSC::MIPSAssembler::cnged):
79	(JSC::MIPSAssembler::cltd):
80	(JSC::MIPSAssembler::cled):
81	(JSC::MIPSAssembler::cueqd):
82	(JSC::MIPSAssembler::coled):
83	(JSC::MIPSAssembler::coltd):
84	(JSC::MIPSAssembler::culed):
85	(JSC::MIPSAssembler::cultd):
86	(JSC::MIPSAssembler::label):
87	(JSC::MIPSAssembler::align):
88	(JSC::MIPSAssembler::getRelocatedAddress):
89	(JSC::MIPSAssembler::getDifferenceBetweenLabels):
90	(JSC::MIPSAssembler::size):
91	(JSC::MIPSAssembler::executableCopy):
92	(JSC::MIPSAssembler::getCallReturnOffset):
93	(JSC::MIPSAssembler::linkJump):
94	(JSC::MIPSAssembler::linkCall):
95	(JSC::MIPSAssembler::linkPointer):
96	(JSC::MIPSAssembler::relinkJump):
97	(JSC::MIPSAssembler::relinkCall):
98	(JSC::MIPSAssembler::repatchInt32):
99	(JSC::MIPSAssembler::repatchPointer):
100	(JSC::MIPSAssembler::repatchLoadPtrToLEA):
101	(JSC::MIPSAssembler::relocateJumps):
102	(JSC::MIPSAssembler::linkWithOffset):
103	(JSC::MIPSAssembler::linkCallInternal):
104	* assembler/MacroAssembler.h:
105	* assembler/MacroAssemblerMIPS.h: Added.
106	(JSC::MacroAssemblerMIPS::MacroAssemblerMIPS):
107	(JSC::MacroAssemblerMIPS::):
108	(JSC::MacroAssemblerMIPS::add32):
109	(JSC::MacroAssemblerMIPS::and32):
110	(JSC::MacroAssemblerMIPS::lshift32):
111	(JSC::MacroAssemblerMIPS::mul32):
112	(JSC::MacroAssemblerMIPS::not32):
113	(JSC::MacroAssemblerMIPS::or32):
114	(JSC::MacroAssemblerMIPS::rshift32):
115	(JSC::MacroAssemblerMIPS::sub32):
116	(JSC::MacroAssemblerMIPS::xor32):
117	(JSC::MacroAssemblerMIPS::load32):
118	(JSC::MacroAssemblerMIPS::load32WithUnalignedHalfWords):
119	(JSC::MacroAssemblerMIPS::load32WithAddressOffsetPatch):
120	(JSC::MacroAssemblerMIPS::loadPtrWithPatchToLEA):
121	(JSC::MacroAssemblerMIPS::loadPtrWithAddressOffsetPatch):
122	(JSC::MacroAssemblerMIPS::load16):
123	(JSC::MacroAssemblerMIPS::store32WithAddressOffsetPatch):
124	(JSC::MacroAssemblerMIPS::store32):
125	(JSC::MacroAssemblerMIPS::supportsFloatingPoint):
126	(JSC::MacroAssemblerMIPS::supportsFloatingPointTruncate):
127	(JSC::MacroAssemblerMIPS::pop):
128	(JSC::MacroAssemblerMIPS::push):
129	(JSC::MacroAssemblerMIPS::move):
130	(JSC::MacroAssemblerMIPS::swap):
131	(JSC::MacroAssemblerMIPS::signExtend32ToPtr):
132	(JSC::MacroAssemblerMIPS::zeroExtend32ToPtr):
133	(JSC::MacroAssemblerMIPS::branch32):
134	(JSC::MacroAssemblerMIPS::branch32WithUnalignedHalfWords):
135	(JSC::MacroAssemblerMIPS::branch16):
136	(JSC::MacroAssemblerMIPS::branchTest32):
137	(JSC::MacroAssemblerMIPS::jump):
138	(JSC::MacroAssemblerMIPS::branchAdd32):
139	(JSC::MacroAssemblerMIPS::branchMul32):
140	(JSC::MacroAssemblerMIPS::branchSub32):
141	(JSC::MacroAssemblerMIPS::breakpoint):
142	(JSC::MacroAssemblerMIPS::nearCall):
143	(JSC::MacroAssemblerMIPS::call):
144	(JSC::MacroAssemblerMIPS::ret):
145	(JSC::MacroAssemblerMIPS::set32):
146	(JSC::MacroAssemblerMIPS::setTest32):
147	(JSC::MacroAssemblerMIPS::moveWithPatch):
148	(JSC::MacroAssemblerMIPS::branchPtrWithPatch):
149	(JSC::MacroAssemblerMIPS::storePtrWithPatch):
150	(JSC::MacroAssemblerMIPS::tailRecursiveCall):
151	(JSC::MacroAssemblerMIPS::makeTailRecursiveCall):
152	(JSC::MacroAssemblerMIPS::loadDouble):
153	(JSC::MacroAssemblerMIPS::storeDouble):
154	(JSC::MacroAssemblerMIPS::addDouble):
155	(JSC::MacroAssemblerMIPS::subDouble):
156	(JSC::MacroAssemblerMIPS::mulDouble):
157	(JSC::MacroAssemblerMIPS::convertInt32ToDouble):
158	(JSC::MacroAssemblerMIPS::insertRelaxationWords):
159	(JSC::MacroAssemblerMIPS::branchTrue):
160	(JSC::MacroAssemblerMIPS::branchFalse):
161	(JSC::MacroAssemblerMIPS::branchEqual):
162	(JSC::MacroAssemblerMIPS::branchNotEqual):
163	(JSC::MacroAssemblerMIPS::branchDouble):
164	(JSC::MacroAssemblerMIPS::branchTruncateDoubleToInt32):
165	(JSC::MacroAssemblerMIPS::linkCall):
166	(JSC::MacroAssemblerMIPS::repatchCall):
167	* jit/ExecutableAllocator.h:
168	(JSC::ExecutableAllocator::cacheFlush):
169	* jit/JIT.h:
170	* jit/JITInlineMethods.h:
171	(JSC::JIT::preserveReturnAddressAfterCall):
172	(JSC::JIT::restoreReturnAddressBeforeReturn):
173	* jit/JITOpcodes.cpp:
174	* jit/JITStubs.cpp:
175	(JSC::JITThunks::JITThunks):
176	* jit/JITStubs.h:
177	(JSC::JITStackFrame::returnAddressSlot):
178	* wtf/Platform.h:
179	* yarr/RegexJIT.cpp:
180	(JSC::Yarr::RegexGenerator::generateEnter):
181	(JSC::Yarr::RegexGenerator::generateReturn):
182
1	2010-02-25 Oliver Hunt <oliver@apple.com>	183	2010-02-25 Oliver Hunt <oliver@apple.com>
2		184
3	Reviewed by Geoff Garen.	185	Reviewed by Geoff Garen.

Lines 43-48 JavaScriptCore/jit/ExecutableAllocator.h_sec1
- JavaScriptCore/jit/ExecutableAllocator.h +30 lines
43	#include <e32std.h>	43	#include <e32std.h>
44	#endif	44	#endif
45		45
		46	#if CPU(MIPS) && OS(LINUX)
		47	#include <sys/cachectl.h>
		48	#endif
		49
46	#if OS(WINCE)	50	#if OS(WINCE)
47	// From pkfuncs.h (private header file from the Platform Builder)	51	// From pkfuncs.h (private header file from the Platform Builder)
48	#define CACHE_SYNC_ALL 0x07F	52	#define CACHE_SYNC_ALL 0x07F
Lines 190-195 public: JavaScriptCore/jit/ExecutableAllocator.h_sec2
190	static void cacheFlush(void*, size_t)	194	static void cacheFlush(void*, size_t)
191	{	195	{
192	}	196	}
		197	#elif CPU(MIPS)
		198	static void cacheFlush(void* code, size_t size)
		199	{
		200	#if COMPILER(GCC) && (GCC_VERSION >= 40300)
		201	#if WTF_MIPS_ISA_REV(2) && (GCC_VERSION < 40403)
		202	int lineSize;
		203	asm ("rdhwr %0, $1" : "=r" (lineSize));
		204	//
		205	// Modify "start" and "end" to avoid GCC 4.3.0-4.4.2 bug in
		206	// mips_expand_synci_loop that may execute synci one more time.
		207	// "start" points to the fisrt byte of the cache line.
		208	// "end" points to the last byte of the line before the last cache line.
		209	// Because size is always a multiple of 4, this is safe to set
		210	// "end" to the last byte.
		211	//
		212	intptr_t start = reinterpret_cast<intptr_t>(code) & (-lineSize);
		213	intptr_t end = ((reinterpret_cast<intptr_t>(code) + size - 1) & (-lineSize)) - 1;
		214	__builtin___clear_cache(reinterpret_cast<char>(start), reinterpret_cast<char>(end));
		215	#else
		216	intptr_t end = reinterpret_cast<intptr_t>(code) + size;
		217	__builtin___clear_cache(reinterpret_cast<char>(code), reinterpret_cast<char>(end));
		218	#endif
		219	#else
		220	_flush_cache(reinterpret_cast<char*>(code), size, BCACHE);
		221	#endif
		222	}
193	#elif CPU(ARM_THUMB2) && OS(IPHONE_OS)	223	#elif CPU(ARM_THUMB2) && OS(IPHONE_OS)
194	static void cacheFlush(void* code, size_t size)	224	static void cacheFlush(void* code, size_t size)
195	{	225	{

Lines 191-196 namespace JSC { JavaScriptCore/jit/JITStubs.h_sec1
- JavaScriptCore/jit/JITStubs.h +24 lines
191	// When JIT code makes a call, it pushes its return address just below the rest of the stack.	191	// When JIT code makes a call, it pushes its return address just below the rest of the stack.
192	ReturnAddressPtr* returnAddressSlot() { return &thunkReturnAddress; }	192	ReturnAddressPtr* returnAddressSlot() { return &thunkReturnAddress; }
193	};	193	};
		194	#elif CPU(MIPS)
		195	struct JITStackFrame {
		196	void* reserved; // Unused
		197	JITStubArg args[6];
		198
		199	void* preservedGP; // store GP when using PIC code
		200	void* preservedS0;
		201	void* preservedS1;
		202	void* preservedS2;
		203	void* preservedReturnAddress;
		204
		205	ReturnAddressPtr thunkReturnAddress;
		206
		207	// These arguments passed in a1..a3 (a0 contained the entry code pointed, which is not preserved)
		208	RegisterFile* registerFile;
		209	CallFrame* callFrame;
		210	JSValue* exception;
		211
		212	// These arguments passed on the stack.
		213	Profiler** enabledProfilerReference;
		214	JSGlobalData* globalData;
		215
		216	ReturnAddressPtr* returnAddressSlot() { return &thunkReturnAddress; }
		217	};
194	#else	218	#else
195	#error "JITStackFrame not defined for this platform."	219	#error "JITStackFrame not defined for this platform."
196	#endif	220	#endif

Lines 104-109 JavaScriptCore/wtf/Platform.h_sec1
- JavaScriptCore/wtf/Platform.h -2 / +22 lines
104	#define WTF_CPU_IA64 1	104	#define WTF_CPU_IA64 1
105	#endif	105	#endif
106		106
		107	/* CPU(MIPS) - MIPS 32-bit */
		108	/* Note: Only O32 ABI is tested, so we enable it for O32 ABI for now. */
		109	#if (defined(mips) \|\| defined(__mips__)) && defined(_ABIO32)
		110	#define WTF_CPU_MIPS 1
		111	#if defined(__MIPSEB__)
		112	#define WTF_CPU_BIG_ENDIAN 1
		113	#endif
		114	#define WTF_MIPS_PIC (defined __PIC__)
		115	#define WTF_MIPS_ARCH __mips
		116	#define WTF_MIPS_ISA(v) (defined WTF_MIPS_ARCH && WTF_MIPS_ARCH == v)
		117	#define WTF_MIPS_ISA_AT_LEAST(v) (defined WTF_MIPS_ARCH && WTF_MIPS_ARCH >= v)
		118	#define WTF_MIPS_ARCH_REV __mips_isa_rev
		119	#define WTF_MIPS_ISA_REV(v) (defined WTF_MIPS_ARCH_REV && WTF_MIPS_ARCH_REV == v)
		120	#define WTF_MIPS_DOUBLE_FLOAT (defined __mips_hard_float && !defined __mips_single_float)
		121	#endif /* MIPS */
		122
107	/* CPU(PPC) - PowerPC 32-bit */	123	/* CPU(PPC) - PowerPC 32-bit */
108	#if defined(__ppc__) \	124	#if defined(__ppc__) \
109	\|\| defined(__PPC__) \	125	\|\| defined(__PPC__) \
Lines 830-836 JavaScriptCore/wtf/Platform.h_sec2
830	#if !defined(WTF_USE_JSVALUE64) && !defined(WTF_USE_JSVALUE32) && !defined(WTF_USE_JSVALUE32_64)	846	#if !defined(WTF_USE_JSVALUE64) && !defined(WTF_USE_JSVALUE32) && !defined(WTF_USE_JSVALUE32_64)
831	#if (CPU(X86_64) && (OS(UNIX) \|\| OS(WINDOWS))) \|\| CPU(IA64) \|\| CPU(ALPHA)	847	#if (CPU(X86_64) && (OS(UNIX) \|\| OS(WINDOWS))) \|\| CPU(IA64) \|\| CPU(ALPHA)
832	#define WTF_USE_JSVALUE64 1	848	#define WTF_USE_JSVALUE64 1
833	#elif CPU(ARM) \|\| CPU(PPC64)	849	#elif CPU(ARM) \|\| CPU(PPC64) \|\| CPU(MIPS)
834	#define WTF_USE_JSVALUE32 1	850	#define WTF_USE_JSVALUE32 1
835	#elif OS(WINDOWS) && COMPILER(MINGW)	851	#elif OS(WINDOWS) && COMPILER(MINGW)
836	/* Using JSVALUE32_64 causes padding/alignement issues for JITStubArg	852	/* Using JSVALUE32_64 causes padding/alignement issues for JITStubArg
Lines 883-888 on MinGW. See https://bugs.webkit.org/sh JavaScriptCore/wtf/Platform.h_sec3
883	#define ENABLE_JIT 1	899	#define ENABLE_JIT 1
884	#elif CPU(ARM_TRADITIONAL) && OS(LINUX)	900	#elif CPU(ARM_TRADITIONAL) && OS(LINUX)
885	#define ENABLE_JIT 1	901	#define ENABLE_JIT 1
		902	#elif CPU(MIPS) && OS(LINUX)
		903	#define ENABLE_JIT 1
		904	#define WTF_USE_JIT_STUB_ARGUMENT_VA_LIST 0
886	#endif	905	#endif
887	#endif /* PLATFORM(QT) */	906	#endif /* PLATFORM(QT) */
888		907
Lines 950-956 on MinGW. See https://bugs.webkit.org/sh JavaScriptCore/wtf/Platform.h_sec4
950	\|\| (CPU(X86) && OS(WINDOWS) && COMPILER(MSVC)) \	969	\|\| (CPU(X86) && OS(WINDOWS) && COMPILER(MSVC)) \
951	\|\| (CPU(X86) && OS(LINUX) && GCC_VERSION >= 40100) \	970	\|\| (CPU(X86) && OS(LINUX) && GCC_VERSION >= 40100) \
952	\|\| (CPU(X86_64) && OS(LINUX) && GCC_VERSION >= 40100) \	971	\|\| (CPU(X86_64) && OS(LINUX) && GCC_VERSION >= 40100) \
953	\|\| (CPU(ARM_TRADITIONAL) && OS(LINUX))	972	\|\| (CPU(ARM_TRADITIONAL) && OS(LINUX)) \
		973	\|\| (CPU(MIPS) && OS(LINUX))
954	#define ENABLE_YARR 1	974	#define ENABLE_YARR 1
955	#define ENABLE_YARR_JIT 1	975	#define ENABLE_YARR_JIT 1
956	#endif	976	#endif